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| author |   Nagarjuna Kristam <nkristam@nvidia.com> | 2020-02-10 13:41:41 +0530 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-03-12 12:14:27 +0100 |
| commit | e74db5a5b4876bfea01ee58f5f2e66af13d7f5cd (patch) | |
| tree | f68e83e4f217ae7f1476a8d07781f69d8ae86176 /arch/arm64/boot/dts/nvidia/tegra210.dtsi | |
| parent | arm64: tegra: Update OTG port entries for Jetson TX2 (diff) | |
| download | linux-dev-e74db5a5b4876bfea01ee58f5f2e66af13d7f5cd.tar.xz linux-dev-e74db5a5b4876bfea01ee58f5f2e66af13d7f5cd.zip | |
arm64: tegra: Add XUDC node for Tegra210
Tegra210 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra210.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c63256ba7f..dfce47b4c657 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1207,6 +1207,25 @@ status = "disabled"; }; + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; + clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra210-mipi"; reg = <0x0 0x700e3000 0x0 0x100>; |