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| author |   Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:07:01 +0800 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-02-07 19:03:56 +0100 |
| commit | d4eb7653a8dcbcff45ace820314d4e8044fe8d38 (patch) | |
| tree | 577b064eb3dbbfe8c62bda5ed997cd3a93d97f71 /arch/arm64/boot/dts/nvidia | |
| parent | arm64: tegra: Add CPU power rail regulator on Smaug (diff) | |
| download | linux-dev-d4eb7653a8dcbcff45ace820314d4e8044fe8d38.tar.xz linux-dev-d4eb7653a8dcbcff45ace820314d4e8044fe8d38.zip | |
arm64: tegra: Enable DFLL clock on Smaug
Enable DFLL clock for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 9a8f6b021323..a4b8f668a6d4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1698,6 +1698,18 @@ status = "okay"; }; + clock@70110000 { + status = "okay"; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,i2c-fs-rate = <400000>; + nvidia,sample-rate = <12500>; + vdd-cpu-supply = <&max77621_cpu>; + }; + aconnect@702c0000 { status = "okay"; |