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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-08-19 11:31:58 +0300 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2022-08-29 16:27:27 -0500 |
| commit | 408c4eadd5d641b899db5eeacc2221273118a287 (patch) | |
| tree | 1cc770a5ba1a1eaf3ad9feeaad4888e32c3692bc /arch/arm64/boot/dts/qcom/msm8998.dtsi | |
| parent | arm64: dts: qcom: msm8998: split TCSR halt regs out of mutex (diff) | |
| download | linux-dev-408c4eadd5d641b899db5eeacc2221273118a287.tar.xz linux-dev-408c4eadd5d641b899db5eeacc2221273118a287.zip | |
arm64: dts: qcom: msm8998: switch TCSR mutex to MMIO
The TCSR mutex bindings allow device to be described only with address
space (so it uses MMIO, not syscon regmap). This seems reasonable as
TCSR mutex is actually a dedicated IO address space and it also fixes DT
schema checks:
qcom/msm8998-asus-novago-tp370ql.dtb: hwlock: 'reg' is a required property
qcom/msm8998-asus-novago-tp370ql.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220819083209.50844-6-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8998.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8998.dtsi | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index eb9552368a54..d463a66715ea 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -308,12 +308,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1047,9 +1041,10 @@ }; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x20000>; + #hwlock-cells = <1>; }; tcsr_regs_1: sycon@1f60000 { |