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author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-08-19 11:32:04 +0300 |
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committer | Bjorn Andersson <andersson@kernel.org> | 2022-08-29 16:27:28 -0500 |
commit | 3ed99307ec842fdb63b1519a011cb74e66b8d9cd (patch) | |
tree | 04d6cc134f14b8c1f0b03ec73c87c8f9def06484 /arch/arm64/boot/dts/qcom/sdm845.dtsi | |
parent | arm64: dts: qcom: sdm845: split TCSR halt regs out of mutex (diff) | |
download | linux-dev-3ed99307ec842fdb63b1519a011cb74e66b8d9cd.tar.xz linux-dev-3ed99307ec842fdb63b1519a011cb74e66b8d9cd.zip |
arm64: dts: qcom: sdm845: switch TCSR mutex to MMIO
The TCSR mutex bindings allow device to be described only with address
space (so it uses MMIO, not syscon regmap). This seems reasonable as
TCSR mutex is actually a dedicated IO address space and it also fixes DT
schema checks:
qcom/sdm845-shift-axolotl.dtb: hwlock: 'reg' is a required property
qcom/sdm845-shift-axolotl.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220819083209.50844-12-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cff96cbbdf28..155e0cf164fc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -919,12 +919,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; @@ -2625,9 +2619,10 @@ status = "disabled"; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; }; tcsr_regs_1: sycon@1f60000 { |