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| author |   Shawn Lin <shawn.lin@rock-chips.com> | 2017-05-16 14:30:40 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2017-05-23 10:37:12 +0200 |
| commit | d633becc583e13b38c4aea53b97a197acd61a521 (patch) | |
| tree | dbb77d6a4098ec5665db0cf526f9eb8efb66e29e /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | arm64: dts: rockchip: add pinctrl settings for some rk3399 peripherals (diff) | |
| download | linux-dev-d633becc583e13b38c4aea53b97a197acd61a521.tar.xz linux-dev-d633becc583e13b38c4aea53b97a197acd61a521.zip | |
arm64: dts: rockchip: extent bus-ranges of PCIe for rk3399
In order to support multiple hierarchy of PCIe buses,
for instance, PCIe switch, we need to extent bus-ranges
to as max as possible. We have 32 regions and could support
up to 31 buses except bus 0 for our root bridge.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 25cb51dd10c5..532b89dd6266 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -220,7 +220,7 @@ #size-cells = <2>; #interrupt-cells = <1>; aspm-no-l0s; - bus-range = <0x0 0x1>; + bus-range = <0x0 0x1f>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf", |