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| author |   Chen-Yu Tsai <wens@csie.org> | 2018-08-24 13:38:49 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2018-09-29 15:57:42 +0200 |
| commit | bb39ed07e55bd56e16993e7d454f649e99c9b7f2 (patch) | |
| tree | 1a8cb8c4619a1a475aeb0ba0105dc8893514d2d2 /arch/arm64/boot | |
| parent | ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support (diff) | |
| download | linux-dev-bb39ed07e55bd56e16993e7d454f649e99c9b7f2.tar.xz linux-dev-bb39ed07e55bd56e16993e7d454f649e99c9b7f2.zip | |
arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
The H5 has a Mali-450 GPU with 4 Pixel Processor cores.
Interestingly, while the datasheet lists an interrupt line for the GPU's
PMU, the hardware block itself doesn't seem to have it. Reads from the
PMU address range all return zero, and writes are ignored.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 62d646baac3c..b41dc1aab67d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -92,6 +92,49 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + + soc { + mali: gpu@1e80000 { + compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; + reg = <0x01e80000 0x30000>; + /* + * While the datasheet lists an interrupt for the + * PMU, the actual silicon does not have the PMU + * block. Reads all return zero, and writes are + * ignored. + */ + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + }; }; &ccu { |