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| author |   Marc Zyngier <marc.zyngier@arm.com> | 2019-05-23 11:24:50 +0100 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2019-05-23 15:40:30 +0100 |
| commit | a5325089bd05a7b0259cc4038479d36308edbda2 (patch) | |
| tree | 253c14c201d292126e4166f88b397642cdedd90c /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64/module: deal with ambiguity in PRELxx relocation ranges (diff) | |
| download | linux-dev-a5325089bd05a7b0259cc4038479d36308edbda2.tar.xz linux-dev-a5325089bd05a7b0259cc4038479d36308edbda2.zip | |
arm64: Handle erratum 1418040 as a superset of erratum 1188873
We already mitigate erratum 1188873 affecting Cortex-A76 and
Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to
r3p1 of the same cores are affected by erratum 1418040, which
has the same workaround as 1188873.
Let's expand the range of affected revisions to match 1418040,
and repaint all occurences of 1188873 to 1418040. Whilst we're
there, do a bit of reformating in silicon-errata.txt and drop
a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 73faee64e498..33401ebc187c 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -53,7 +53,7 @@ #define ARM64_HAS_STAGE2_FWB 32 #define ARM64_HAS_CRC32 33 #define ARM64_SSBS 34 -#define ARM64_WORKAROUND_1188873 35 +#define ARM64_WORKAROUND_1418040 35 #define ARM64_HAS_SB 36 #define ARM64_WORKAROUND_1165522 37 #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 |