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authorMark Brown <broonie@kernel.org>2022-02-07 15:20:32 +0000
committerWill Deacon <will@kernel.org>2022-02-25 14:28:18 +0000
commit0a2eec83c2c23cf609e781732b338a9a4f18e00c (patch)
tree250b6b2c6104bc0e3f1b739cd23290b3108a0cb5 /arch/arm64/include/asm/cpufeature.h
parentarm64: Always use individual bits in CPACR floating point enables (diff)
downloadlinux-dev-0a2eec83c2c23cf609e781732b338a9a4f18e00c.tar.xz
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arm64: cpufeature: Always specify and use a field width for capabilities
Since all the fields in the main ID registers are 4 bits wide we have up until now not bothered specifying the width in the code. Since we now wish to use this mechanism to enumerate features from the floating point feature registers which do not follow this pattern add a width to the table. This means updating all the existing table entries but makes it less likely that we run into issues in future due to implicitly assuming a 4 bit width. Signed-off-by: Mark Brown <broonie@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220207152109.197566-4-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/cpufeature.h')
-rw-r--r--arch/arm64/include/asm/cpufeature.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index ef6be92b1921..2728abd9cae4 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -356,6 +356,7 @@ struct arm64_cpu_capabilities {
struct { /* Feature register checking */
u32 sys_reg;
u8 field_pos;
+ u8 field_width;
u8 min_field_value;
u8 hwcap_type;
bool sign;