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| author |   Will Deacon <will.deacon@arm.com> | 2018-12-13 15:34:44 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-13 15:34:44 +0000 |
| commit | 26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce (patch) | |
| tree | ec8589936bb72ff721ddcb37cc9682fc572ce3d4 /arch/arm64/include/asm/esr.h | |
| parent | arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field (diff) | |
| download | linux-dev-26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce.tar.xz linux-dev-26a25c841d9e6ba4ceba4b8d7ce3f3227f7510ce.zip | |
arm64: perf: Treat EXCLUDE_EL* bit definitions as unsigned
Although the upper 32 bits of the PMEVTYPER<n>_EL0 registers are RES0,
we should treat the EXCLUDE_EL* bit definitions as unsigned so that we
avoid accidentally sign-extending the privilege filtering bit (bit 31)
into the upper half of the register.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/esr.h')
0 files changed, 0 insertions, 0 deletions