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author | Paolo Bonzini <pbonzini@redhat.com> | 2018-12-19 20:33:55 +0100 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-12-19 20:33:55 +0100 |
commit | 8c5e14f438b8cee47ff01fc1cadd15e3eed44b59 (patch) | |
tree | 8f5028e0fce8f3a73cb000b47e571f3788429d23 /arch/arm64/include/asm/stage2_pgtable.h | |
parent | kvm: selftests: ucall: improve ucall placement in memory, fix unsigned comparison (diff) | |
parent | arm: KVM: Add S2_PMD_{MASK,SIZE} constants (diff) | |
download | linux-dev-8c5e14f438b8cee47ff01fc1cadd15e3eed44b59.tar.xz linux-dev-8c5e14f438b8cee47ff01fc1cadd15e3eed44b59.zip |
Merge tag 'kvmarm-for-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm updates for 4.21
- Large PUD support for HugeTLB
- Single-stepping fixes
- Improved tracing
- Various timer and vgic fixups
Diffstat (limited to 'arch/arm64/include/asm/stage2_pgtable.h')
-rw-r--r-- | arch/arm64/include/asm/stage2_pgtable.h | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h index d352f6df8d2c..5412fa40825e 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -30,16 +30,14 @@ #define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) /* - * The hardware supports concatenation of up to 16 tables at stage2 entry level - * and we use the feature whenever possible. + * The hardware supports concatenation of up to 16 tables at stage2 entry + * level and we use the feature whenever possible, which means we resolve 4 + * additional bits of address at the entry level. * - * Now, the minimum number of bits resolved at any level is (PAGE_SHIFT - 3). - * On arm64, the smallest PAGE_SIZE supported is 4k, which means - * (PAGE_SHIFT - 3) > 4 holds for all page sizes. - * This implies, the total number of page table levels at stage2 expected - * by the hardware is actually the number of levels required for (IPA_SHIFT - 4) - * in normal translations(e.g, stage1), since we cannot have another level in - * the range (IPA_SHIFT, IPA_SHIFT - 4). + * This implies, the total number of page table levels required for + * IPA_SHIFT at stage2 expected by the hardware can be calculated using + * the same logic used for the (non-collapsable) stage1 page tables but for + * (IPA_SHIFT - 4). */ #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) |