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| author |   Mark Brown <broonie@kernel.org> | 2022-09-05 23:54:20 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2022-09-09 10:59:05 +0100 |
| commit | cfa3a6c55b61a062afa1ccd8bca45fd270dd3d0f (patch) | |
| tree | a8fdc4a0049dc4c57f5bce2e10c5e46bdf11ee29 /arch/arm64/include/asm/sysreg.h | |
| parent | arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation (diff) | |
| download | linux-dev-cfa3a6c55b61a062afa1ccd8bca45fd270dd3d0f.tar.xz linux-dev-cfa3a6c55b61a062afa1ccd8bca45fd270dd3d0f.zip | |
arm64/sysreg: Convert ID_AA64MMFR2_EL1 to automatic generation
Convert ID_AA64MMFR2_EL1 defines to automatic generation as per DDI0487H.a,
no functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-24-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 5dcd8dff53b3..62c5c596b18f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -199,8 +199,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) - #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) @@ -749,23 +747,6 @@ #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 #endif -/* id_aa64mmfr2 */ -#define ID_AA64MMFR2_EL1_E0PD_SHIFT 60 -#define ID_AA64MMFR2_EL1_EVT_SHIFT 56 -#define ID_AA64MMFR2_EL1_BBM_SHIFT 52 -#define ID_AA64MMFR2_EL1_TTL_SHIFT 48 -#define ID_AA64MMFR2_EL1_FWB_SHIFT 40 -#define ID_AA64MMFR2_EL1_IDS_SHIFT 36 -#define ID_AA64MMFR2_EL1_AT_SHIFT 32 -#define ID_AA64MMFR2_EL1_ST_SHIFT 28 -#define ID_AA64MMFR2_EL1_NV_SHIFT 24 -#define ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 -#define ID_AA64MMFR2_EL1_VARange_SHIFT 16 -#define ID_AA64MMFR2_EL1_IESB_SHIFT 12 -#define ID_AA64MMFR2_EL1_LSM_SHIFT 8 -#define ID_AA64MMFR2_EL1_UAO_SHIFT 4 -#define ID_AA64MMFR2_EL1_CnP_SHIFT 0 - /* id_aa64dfr0 */ #define ID_AA64DFR0_MTPMU_SHIFT 48 #define ID_AA64DFR0_TRBE_SHIFT 44 |