diff options
| author |   Shannon Zhao <shannon.zhao@linaro.org> | 2015-10-28 12:10:30 +0800 |
|---|---|---|
| committer |   Marc Zyngier <marc.zyngier@arm.com> | 2016-02-29 18:34:21 +0000 |
| commit | 76993739cd6f5b42e881fe3332b9f8eb98cd6907 (patch) | |
| tree | c2a3e47cacfff585748d69b685c6c8a2e5a390e4 /arch/arm64/include | |
| parent | arm64: KVM: Add access handler for PMSWINC register (diff) | |
| download | linux-dev-76993739cd6f5b42e881fe3332b9f8eb98cd6907.tar.xz linux-dev-76993739cd6f5b42e881fe3332b9f8eb98cd6907.zip | |
arm64: KVM: Add helper to handle PMCR register bits
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/kvm_perf_event.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/kvm_perf_event.h b/arch/arm64/include/asm/kvm_perf_event.h index 62fa60fbc0b3..6d080c07873b 100644 --- a/arch/arm64/include/asm/kvm_perf_event.h +++ b/arch/arm64/include/asm/kvm_perf_event.h @@ -29,9 +29,11 @@ #define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ #define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */ #define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +/* Determines which bit of PMCCNTR_EL0 generates an overflow */ +#define ARMV8_PMU_PMCR_LC (1 << 6) #define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */ #define ARMV8_PMU_PMCR_N_MASK 0x1f -#define ARMV8_PMU_PMCR_MASK 0x3f /* Mask for writable bits */ +#define ARMV8_PMU_PMCR_MASK 0x7f /* Mask for writable bits */ /* * PMOVSR: counters overflow flag status reg |