diff options
| author |   Mark Rutland <mark.rutland@arm.com> | 2017-02-09 15:19:20 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2017-02-15 12:20:29 +0000 |
| commit | 521c646108ed199d19c5c73978aaca3e18ca8f81 (patch) | |
| tree | 1ec326a30049bf907bd669bbc3c69cb3acbec7c9 /arch/arm64/kernel/cpufeature.c | |
| parent | arm64: traps: correctly handle MRS/MSR with XZR (diff) | |
| download | linux-dev-521c646108ed199d19c5c73978aaca3e18ca8f81.tar.xz linux-dev-521c646108ed199d19c5c73978aaca3e18ca8f81.zip | |
arm64: cpufeature: correctly handle MRS to XZR
In emulate_mrs() we may erroneously write back to the user SP rather
than XZR if we trap an MRS instruction where Xt == 31.
Use the new pt_regs_write_reg() helper to handle this correctly.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Fixes: 77c97b4ee21290f5 ("arm64: cpufeature: Expose CPUID registers by emulation")
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1ee5357d0c6a..abda8e861865 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1214,7 +1214,7 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) rc = emulate_sys_reg(sys_reg, &val); if (!rc) { dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); - regs->user_regs.regs[dst] = val; + pt_regs_write_reg(regs, dst, val); regs->pc += 4; } |