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| author |   Dave Martin <Dave.Martin@arm.com> | 2018-05-14 18:51:09 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2018-05-17 18:19:53 +0100 |
| commit | 159fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b (patch) | |
| tree | 2cc7356909e076e77d1fe961f9c90f2f0c8f0595 /arch/arm64/kernel | |
| parent | arm64: topology: divorce MC scheduling domain from core_siblings (diff) | |
| download | linux-dev-159fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b.tar.xz linux-dev-159fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b.zip | |
arm64/sve: Write ZCR_EL1 on context switch only if changed
Writes to ZCR_EL1 are self-synchronising, and so may be expensive
in typical implementations.
This patch adopts the approach used for costly system register
writes elsewhere in the kernel: the system register write is
suppressed if it would not change the stored value.
Since the common case will be that of switching between tasks that
use the same vector length as one another, prediction hit rates on
the conditional branch should be reasonably good, with lower
expected amortised cost than the unconditional execution of a
heavyweight self-synchronising instruction.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
| -rw-r--r-- | arch/arm64/kernel/entry-fpsimd.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index 73f17bffcd23..12d4958e6429 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -49,7 +49,7 @@ ENTRY(sve_save_state) ENDPROC(sve_save_state) ENTRY(sve_load_state) - sve_load 0, x1, x2, 3 + sve_load 0, x1, x2, 3, x4 ret ENDPROC(sve_load_state) |