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| author |   Catalin Marinas <catalin.marinas@arm.com> | 2018-02-28 18:47:20 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2018-03-06 18:52:32 +0000 |
| commit | 1f85b42a691cd8329ba82dbcaeec80ac1231b32a (patch) | |
| tree | da12a0975152204ecccb02c335e68cb3f09aed22 /arch/arm64/kernel | |
| parent | arm64: lse: Pass -fomit-frame-pointer to out-of-line ll/sc atomics (diff) | |
| download | linux-dev-1f85b42a691cd8329ba82dbcaeec80ac1231b32a.tar.xz linux-dev-1f85b42a691cd8329ba82dbcaeec80ac1231b32a.zip | |
arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)
Commit 97303480753e ("arm64: Increase the max granular size") increased
the cache line size to 128 to match Cavium ThunderX, apparently for some
performance benefit which could not be confirmed. This change, however,
has an impact on the network packets allocation in certain
circumstances, requiring slightly over a 4K page with a significant
performance degradation.
This patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache line) while
keeping ARCH_DMA_MINALIGN at 128. The cache_line_size() function was
changed to default to ARCH_DMA_MINALIGN in the absence of a meaningful
CTR_EL0.CWG bit field.
In addition, if a system with ARCH_DMA_MINALIGN < CTR_EL0.CWG is
detected, the kernel will force swiotlb bounce buffering for all
non-coherent devices since DMA cache maintenance on sub-CWG ranges is
not safe, leading to data corruption.
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Cc: Timur Tabi <timur@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3c7dfaf24d6c..f96b3449034b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1382,7 +1382,6 @@ bool this_cpu_has_cap(unsigned int cap) void __init setup_cpu_features(void) { u32 cwg; - int cls; /* Set the CPU feature capabilies */ setup_feature_capabilities(); @@ -1405,13 +1404,9 @@ void __init setup_cpu_features(void) * Check for sane CTR_EL0.CWG value. */ cwg = cache_type_cwg(); - cls = cache_line_size(); if (!cwg) - pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", - cls); - if (L1_CACHE_BYTES < cls) - pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", - L1_CACHE_BYTES, cls); + pr_warn("No Cache Writeback Granule information, assuming %d\n", + ARCH_DMA_MINALIGN); } static bool __maybe_unused |