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| author |   Oliver Upton <oupton@google.com> | 2022-05-03 06:02:02 +0000 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2022-05-03 11:14:34 +0100 |
| commit | 9369bc5c5e35985f38d04bd98c6d28a032e84b17 (patch) | |
| tree | 464983c7edc9a6f52eef313cc6f8dcd313eb895d /arch/arm64/kvm/handle_exit.c | |
| parent | KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents (diff) | |
| download | linux-dev-9369bc5c5e35985f38d04bd98c6d28a032e84b17.tar.xz linux-dev-9369bc5c5e35985f38d04bd98c6d28a032e84b17.zip | |
KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler
In order to enable HCR_EL2.TID3 for AArch32 guests KVM needs to handle
traps where ESR_EL2.EC=0x8, which corresponds to an attempted VMRS
access from an ID group register. Specifically, the MVFR{0-2} registers
are accessed this way from AArch32. Conveniently, these registers are
architecturally mapped to MVFR{0-2}_EL1 in AArch64. Furthermore, KVM
already handles reads to these aliases in AArch64.
Plumb VMRS read traps through to the general AArch64 system register
handler.
Signed-off-by: Oliver Upton <oupton@google.com>
Reviewed-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220503060205.2823727-5-oupton@google.com
Diffstat (limited to 'arch/arm64/kvm/handle_exit.c')
| -rw-r--r-- | arch/arm64/kvm/handle_exit.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 97fe14aab1a3..5088a86ace5b 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -167,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = { [ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64, [ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32, [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store, + [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id, [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64, [ESR_ELx_EC_HVC32] = handle_hvc, [ESR_ELx_EC_SMC32] = handle_smc, |