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| author |   Fuad Tabba <tabba@google.com> | 2021-05-24 09:29:58 +0100 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2021-05-25 19:27:49 +0100 |
| commit | 406d7d4e2bc76d38a6dc88733a0f72fabf02d305 (patch) | |
| tree | 932f749a4a37b29ac1b75d3c8a48278b8fccd0f8 /arch/arm64/mm/cache.S | |
| parent | arm64: __clean_dcache_area_pop to take end parameter instead of size (diff) | |
| download | linux-dev-406d7d4e2bc76d38a6dc88733a0f72fabf02d305.tar.xz linux-dev-406d7d4e2bc76d38a6dc88733a0f72fabf02d305.zip | |
arm64: __clean_dcache_area_pou to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.
No functional change intended.
Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-16-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index b71fcf56516b..ea605d94182f 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -113,20 +113,19 @@ SYM_FUNC_START_PI(__flush_dcache_area) SYM_FUNC_END_PI(__flush_dcache_area) /* - * __clean_dcache_area_pou(kaddr, size) + * __clean_dcache_area_pou(start, end) * - * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) + * Ensure that any D-cache lines for the interval [start, end) * are cleaned to the PoU. * - * - kaddr - kernel address - * - size - size in question + * - start - virtual start address of region + * - end - virtual end address of region */ SYM_FUNC_START(__clean_dcache_area_pou) alternative_if ARM64_HAS_CACHE_IDC dsb ishst ret alternative_else_nop_endif - add x1, x0, x1 dcache_by_line_op cvau, ish, x0, x1, x2, x3 ret SYM_FUNC_END(__clean_dcache_area_pou) |