diff options
| author |   Catalin Marinas <catalin.marinas@arm.com> | 2017-12-22 17:40:58 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-12-22 17:40:58 +0000 |
| commit | 1f911c3a1140e1668e68791fb6dd07757e2f3956 (patch) | |
| tree | 5ff4161bd109c2b54e538fae78877c7626e56af5 /arch/arm64/mm/proc.S | |
| parent | Merge branch 'kpti' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux (diff) | |
| parent | arm64: enable 52-bit physical address support (diff) | |
| download | linux-dev-1f911c3a1140e1668e68791fb6dd07757e2f3956.tar.xz linux-dev-1f911c3a1140e1668e68791fb6dd07757e2f3956.zip | |
Merge branch 'for-next/52-bit-pa' into for-next/core
* for-next/52-bit-pa:
arm64: enable 52-bit physical address support
arm64: allow ID map to be extended to 52 bits
arm64: handle 52-bit physical addresses in page table entries
arm64: don't open code page table entry creation
arm64: head.S: handle 52-bit PAs in PTEs in early page table setup
arm64: handle 52-bit addresses in TTBR
arm64: limit PA size to supported range
arm64: add kconfig symbol to configure physical address size
Diffstat (limited to 'arch/arm64/mm/proc.S')
| -rw-r--r-- | arch/arm64/mm/proc.S | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 3146dc96f05b..bc334588f234 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -143,7 +143,8 @@ ENTRY(cpu_do_switch_mm) bfi x2, x1, #48, #16 // set the ASID msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) isb - msr ttbr0_el1, x0 // now update TTBR0 + phys_to_ttbr x0, x2 + msr ttbr0_el1, x2 // now update TTBR0 isb post_ttbr_update_workaround ret @@ -160,14 +161,16 @@ ENTRY(idmap_cpu_replace_ttbr1) save_and_disable_daif flags=x2 adrp x1, empty_zero_page - msr ttbr1_el1, x1 + phys_to_ttbr x1, x3 + msr ttbr1_el1, x3 isb tlbi vmalle1 dsb nsh isb - msr ttbr1_el1, x0 + phys_to_ttbr x0, x3 + msr ttbr1_el1, x3 isb restore_daif x2 @@ -230,11 +233,9 @@ ENTRY(__cpu_setup) tcr_set_idmap_t0sz x10, x9 /* - * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in - * TCR_EL1. + * Set the IPS bits in TCR_EL1. */ - mrs x9, ID_AA64MMFR0_EL1 - bfi x10, x9, #32, #3 + tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6 #ifdef CONFIG_ARM64_HW_AFDBM /* * Hardware update of the Access and Dirty bits. |