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| author |   Will Deacon <will.deacon@arm.com> | 2013-06-12 16:28:04 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2013-09-03 10:18:02 +0100 |
| commit | d50240a5f6ceaf690a77b0fccb17be51cfa151c2 (patch) | |
| tree | 843603100f6987bf50a4e40713121c1e2a323b7f /arch/arm64/mm | |
| parent | Move the EM_ARM and EM_AARCH64 definitions to uapi/linux/elf-em.h (diff) | |
| download | linux-dev-d50240a5f6ceaf690a77b0fccb17be51cfa151c2.tar.xz linux-dev-d50240a5f6ceaf690a77b0fccb17be51cfa151c2.zip | |
arm64: mm: permit use of tagged pointers at EL0
TCR.TBI0 can be used to cause hardware address translation to ignore the
top byte of userspace virtual addresses. Whilst not especially useful in
standard C programs, this can be used by JITs to `tag' pointers with
various pieces of metadata.
This patch enables this bit for AArch64 Linux, and adds a new file to
Documentation/arm64/ which describes some potential caveats when using
tagged virtual addresses.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/proc.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f84fcf71f129..b1b31bbc967b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -147,7 +147,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ - TCR_ASID16 | (1 << 31) + TCR_ASID16 | TCR_TBI0 | (1 << 31) #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K orr x10, x10, TCR_TG1_64K |