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| author |   Will Deacon <will.deacon@arm.com> | 2015-10-27 12:05:55 +0000 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2015-10-28 18:32:12 +0000 |
| commit | 59f2413573e4ee1e76062beef4a359156500db94 (patch) | |
| tree | b5654cbefa10c97754c4da11b30bcbeb50de1a64 /arch/arm64 | |
| parent | arm64: cpufeature: declare enable_cpu_capabilities as static (diff) | |
| download | linux-dev-59f2413573e4ee1e76062beef4a359156500db94.tar.xz linux-dev-59f2413573e4ee1e76062beef4a359156500db94.zip | |
arm64: cachetype: fix definitions of ICACHEF_* flags
test_bit and set_bit take the bit number to operate on, rather than a
mask. This patch fixes the ICACHEF_* definitions so that they represent
the bit index in __icache_flags as opposed to the mask returned by the
BIT macro.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/include/asm/cachetype.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index da2fc9e3cedd..f5588692f1d4 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -34,8 +34,8 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) -#define ICACHEF_ALIASING BIT(0) -#define ICACHEF_AIVIVT BIT(1) +#define ICACHEF_ALIASING 0 +#define ICACHEF_AIVIVT 1 extern unsigned long __icache_flags; |