diff options
author | Olof Johansson <olof@lixom.net> | 2020-01-16 15:46:05 -0800 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2020-01-16 15:46:06 -0800 |
commit | 116a4b85f6fb0482721a1a4fc1eacb97572e48cd (patch) | |
tree | de3f3dcbf66fa50527e51b2399ff72c3392804c1 /arch/arm | |
parent | Merge tag 'qcom-arm64-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt (diff) | |
parent | ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx (diff) | |
download | linux-dev-116a4b85f6fb0482721a1a4fc1eacb97572e48cd.tar.xz linux-dev-116a4b85f6fb0482721a1a4fc1eacb97572e48cd.zip |
Merge tag 'qcom-dts-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM dts updates for v5.6
* Add SAW L2 nodes to boot secondary cpus on IPQ40xx
* Fix remaining IRQ_TYPE_NONE on APQ8084
* Update tsens node to new style
* Add modem remoteproc node to MSM8974
* Move ADSP SMD edge into ADSP remoteproc node for MSM8974
* Add and enable wireless communication subsystem on MSM8974 and Fairphone 2
* Add MSM8974 interconnect provider nodes
* Add MSM8974 OCMEM node
* tag 'qcom-dts-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx
ARM: dts: qcom: apq8084: Remove all instances of IRQ_TYPE_NONE
ARM: dts: qcom: apq8084: Change tsens definition to new style
ARM: dts: msm8974: Move ADSP smd edge to ADSP PIL
ARM: dts: msm8974: Add modem remoteproc node
ARM: dts: msm8974-FP2: Introduce the wcnss remoteproc node
ARM: dts: msm8974: Introduce the wcnss remoteproc node
ARM: dts: qcom: msm8974: add interconnect nodes
ARM: dts: qcom: msm8974: add ocmem node
Link: https://lore.kernel.org/r/20200113204448.GE3325@yoga
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/qcom-apq8084.dtsi | 44 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 45 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 222 |
4 files changed, 280 insertions, 38 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0a0fb147ebb9..fa1852eed37b 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-apq8084.h> #include <dt-bindings/gpio/gpio.h> @@ -184,7 +185,7 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; + interrupts = <GIC_PPI 7 0xf04>; }; clocks { @@ -203,10 +204,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; + interrupts = <GIC_PPI 2 0xf08>, + <GIC_PPI 3 0xf08>, + <GIC_PPI 4 0xf08>, + <GIC_PPI 1 0xf08>; clock-frequency = <19200000>; }; @@ -253,12 +254,13 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; - timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -269,50 +271,50 @@ frame@f9021000 { frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9021000 0x1000>, <0xf9022000 0x1000>; }; frame@f9023000 { frame-number = <1>; - interrupts = <0 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9023000 0x1000>; status = "disabled"; }; frame@f9024000 { frame-number = <2>; - interrupts = <0 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9024000 0x1000>; status = "disabled"; }; frame@f9025000 { frame-number = <3>; - interrupts = <0 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9025000 0x1000>; status = "disabled"; }; frame@f9026000 { frame-number = <4>; - interrupts = <0 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9026000 0x1000>; status = "disabled"; }; frame@f9027000 { frame-number = <5>; - interrupts = <0 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9027000 0x1000>; status = "disabled"; }; frame@f9028000 { frame-number = <6>; - interrupts = <0 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9028000 0x1000>; status = "disabled"; }; @@ -404,13 +406,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 208 0>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; }; blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; - interrupts = <0 114 0x0>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -420,7 +422,7 @@ compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, @@ -433,7 +435,7 @@ compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>, @@ -449,7 +451,7 @@ <0xfc4cb000 0x1000>, <0xfc4ca000 0x1000>; interrupt-names = "periph_irq"; - interrupts = <0 190 0>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; @@ -463,7 +465,7 @@ compatible = "qcom,smd"; rpm { - interrupts = <0 168 1>; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 8ef26da32ff4..71bb25a8afc0 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -102,6 +102,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + qcom,saw = <&saw_l2>; }; }; @@ -353,6 +354,12 @@ regulator; }; + saw_l2: regulator@b012000 { + compatible = "qcom,saw2"; + reg = <0xb012000 0x1000>; + regulator; + }; + blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts index 26160394d717..d2d48770ec0f 100644 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts @@ -259,6 +259,25 @@ status = "ok"; }; + remoteproc@fb21b000 { + status = "ok"; + + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "ok"; + }; + }; + }; + pinctrl@fd510000 { sdhc1_pin_a: sdhc1-pin-active { clk { @@ -287,6 +306,32 @@ bias-pull-up; }; }; + + wcnss_pin_a: wcnss-pin-active { + wlan { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + + drive-strength = <6>; + bias-pull-down; + }; + + bt { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + + drive-strength = <2>; + bias-pull-down; + }; + + fm { + pins = "gpio41", "gpio42"; + function = "fm"; + + drive-strength = <2>; + bias-pull-down; + }; + }; }; sdhci@f9824900 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9a84eb0cbbe6..4b161b809dd5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include <dt-bindings/interconnect/qcom,msm8974.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> @@ -20,17 +21,17 @@ #size-cells = <1>; ranges; - mpss@8000000 { + mpss_region: mpss@8000000 { reg = <0x08000000 0x5100000>; no-map; }; - mba@d100000 { + mba_region: mba@d100000 { reg = <0x0d100000 0x100000>; no-map; }; - reserved@d200000 { + wcnss_region: wcnss@d200000 { reg = <0x0d200000 0xa00000>; no-map; }; @@ -61,8 +62,11 @@ }; rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; reg = <0x0fd80000 0x180000>; no-map; + + qcom,client-id = <1>; }; }; @@ -356,6 +360,15 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; }; smem { @@ -795,6 +808,119 @@ clock-names = "core"; }; + remoteproc@fc880000 { + compatible = "qcom,msm8974-mss-pil"; + reg = <0xfc880000 0x100>, <0xfc820000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + + pronto: remoteproc@fb21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_region>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + vddpx-supply = <&pm8941_s3>; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3680"; + + clocks = <&rpmcc RPM_SMD_CXO_A2>; + clock-names = "xo"; + + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + status = "disabled"; + + qcom,mmio = <&pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; + msmgpio: pinctrl@fd510000 { compatible = "qcom,msm8974-pinctrl"; reg = <0xfd510000 0x4000>; @@ -1179,6 +1305,79 @@ }; }; + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", + "mem"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", + "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; + }; + }; + + bimc: interconnect@fc380000 { + reg = <0xfc380000 0x6a000>; + compatible = "qcom,msm8974-bimc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + snoc: interconnect@fc460000 { + reg = <0xfc460000 0x4000>; + compatible = "qcom,msm8974-snoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + pnoc: interconnect@fc468000 { + reg = <0xfc468000 0x4000>; + compatible = "qcom,msm8974-pnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PNOC_CLK>, + <&rpmcc RPM_SMD_PNOC_A_CLK>; + }; + + ocmemnoc: interconnect@fc470000 { + reg = <0xfc470000 0x4000>; + compatible = "qcom,msm8974-ocmemnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; + }; + + mmssnoc: interconnect@fc478000 { + reg = <0xfc478000 0x4000>; + compatible = "qcom,msm8974-mmssnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&mmcc MMSS_S0_AXI_CLK>, + <&mmcc MMSS_S0_AXI_CLK>; + }; + + cnoc: interconnect@fc480000 { + reg = <0xfc480000 0x4000>; + compatible = "qcom,msm8974-cnoc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + mdss: mdss@fd900000 { status = "disabled"; @@ -1225,6 +1424,9 @@ "core", "vsync"; + interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; + interconnect-names = "mdp0-mem"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1325,20 +1527,6 @@ smd { compatible = "qcom,smd"; - adsp { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; - }; - - modem { - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - }; - rpm { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; |