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| author |   Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2016-04-12 10:33:52 +0100 |
|---|---|---|
| committer |   Andy Gross <andy.gross@linaro.org> | 2016-04-20 15:03:11 -0500 |
| commit | e4b01fda5dca99c227494bd9dc3a9d7628a17c2f (patch) | |
| tree | 71ff77f33a9dfb1706c2cd5661c443f22dc75cb7 /arch/arm | |
| parent | ARM: dts: apq8064: add support to gsbi1 uart (diff) | |
| download | linux-dev-e4b01fda5dca99c227494bd9dc3a9d7628a17c2f.tar.xz linux-dev-e4b01fda5dca99c227494bd9dc3a9d7628a17c2f.zip | |
ARM: dts: apq8064: add gsbi7 i2c support
This patch adds support to gsbi7 i2c which is used in some of the new
boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 25 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 13 |
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index 8bb5e5f3d07a..4102a98f475b 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -219,4 +219,29 @@ function = "gsbi7"; }; }; + + i2c7_pins: i2c7 { + mux { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + }; + + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c7_pins_sleep: i2c7_pins_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 407a072dea69..b176c094cd6f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -511,6 +511,19 @@ clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c7_pins>; + pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; rng@1a500000 { |