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| author |   Sonic Zhang <sonic.zhang@analog.com> | 2009-12-09 07:01:50 +0000 |
|---|---|---|
| committer |   Mike Frysinger <vapier@gentoo.org> | 2010-03-09 00:30:46 -0500 |
| commit | 5792ab2a0a22fdaef33056ca2b31847a28b1af60 (patch) | |
| tree | 7c1257f6f0fa2c0bf469cb898b38b9320f57920c /arch/blackfin/kernel/cplb-mpu | |
| parent | Blackfin: extend bfin-lq035q1-fb resources to include PPI mode (diff) | |
| download | linux-dev-5792ab2a0a22fdaef33056ca2b31847a28b1af60.tar.xz linux-dev-5792ab2a0a22fdaef33056ca2b31847a28b1af60.zip | |
Blackfin: MPU: handle caches for reserved memory
We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=). The no-MPU code already takes care
of this, so add support to the MPU code as well.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/kernel/cplb-mpu')
| -rw-r--r-- | arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index d4cc53a0ef89..7e6383dc7b20 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -131,7 +131,9 @@ static noinline int dcplb_miss(unsigned int cpu) } else return CPLB_PROT_VIOL; } else if (addr >= _ramend) { - d_data |= CPLB_USER_RD | CPLB_USER_WR; + d_data |= CPLB_USER_RD | CPLB_USER_WR; + if (reserved_mem_dcache_on) + d_data |= CPLB_L1_CHBL; } else { mask = current_rwx_mask[cpu]; if (mask) { @@ -231,6 +233,8 @@ static noinline int icplb_miss(unsigned int cpu) return CPLB_PROT_VIOL; } else if (addr >= _ramend) { i_data |= CPLB_USER_RD; + if (reserved_mem_icache_on) + i_data |= CPLB_L1_CHBL; } else { /* * Two cases to distinguish - a supervisor access must |