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authorArnd Bergmann <arnd@arndb.de>2018-03-07 22:23:24 +0100
committerArnd Bergmann <arnd@arndb.de>2018-03-16 10:55:47 +0100
commit4ba66a9760722ccbb691b8f7116cad2f791cca7b (patch)
treee29f9624ad0b13aa11860e39440bbc5e24d18a30 /arch/blackfin/lib/outs.S
parentarch: remove score port (diff)
downloadlinux-dev-4ba66a9760722ccbb691b8f7116cad2f791cca7b.tar.xz
linux-dev-4ba66a9760722ccbb691b8f7116cad2f791cca7b.zip
arch: remove blackfin port
The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu <Aaron.Wu@analog.com> Acked-by: Bryan Wu <cooloney@gmail.com> Cc: Steven Miao <realmz6@gmail.com> Cc: Mike Frysinger <vapier@chromium.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/blackfin/lib/outs.S')
-rw-r--r--arch/blackfin/lib/outs.S68
1 files changed, 0 insertions, 68 deletions
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 06a5e674401f..000000000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-ENTRY(_outsl)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-1: RTS;
-ENDPROC(_outsl)
-
-ENTRY(_outsw)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw)
-
-ENTRY(_outsb)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-1: RTS;
-ENDPROC(_outsb)
-
-ENTRY(_outsw_8)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw_8)