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authorMike Frysinger <vapier@gentoo.org>2009-10-15 03:45:47 +0000
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:40 -0500
commitcd32cc73625641c068393978e7bb337d29c0cd29 (patch)
tree2919e991260ccb6603b9ac713cd0dff5f83d8854 /arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
parentBlackfin: BF51x: dump non-existent SPI/NFC MMRs (diff)
downloadlinux-dev-cd32cc73625641c068393978e7bb337d29c0cd29.tar.xz
linux-dev-cd32cc73625641c068393978e7bb337d29c0cd29.zip
Blackfin: punt OTP MMRs
People should not be accessing OTP MMRs directly. They should instead go through the Blackfin ROM helper functions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF54x_base.h')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h30
1 files changed, 0 insertions, 30 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 3ce5ce6c4971..f07c0f76e6d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2143,36 +2143,6 @@
#define DPRESCALE 0xf /* Load Counter Register */
-/* Bit masks for OTP_CONTROL */
-
-#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
-#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
-#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
-#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
-#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
-#define FWREN 0x8000 /* OTP/Fuse Write Enable */
-
-/* Bit masks for OTP_BEN */
-
-#define FBEN 0xffff /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define FCOMP 0x1 /* OTP/Fuse Access Complete */
-#define FERROR 0x2 /* OTP/Fuse Access Error */
-#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
-#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
-#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
-
-/* Bit masks for OTP_TIMING */
-
-#define USECDIV 0xff /* Micro Second Divider */
-#define READACC 0x7f00 /* Read Access Time */
-#define CPUMPRL 0x38000 /* Charge Pump Release Time */
-#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
-#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
-#define PGMTIME 0xff000000 /* Program Time */
-
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */