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| author |   Mike Frysinger <vapier@gentoo.org> | 2009-09-14 19:42:26 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-09-16 22:10:49 -0400 |
| commit | ea426e6c62d0f742d87451adc47e91d87b9c3d27 (patch) | |
| tree | cfcb35af1e4eeae5be2a446ec8c8b2d51b421bd8 /arch/blackfin/mach-common/cache-c.c | |
| parent | Blackfin: swap clocksource ratings for gptimer/cycles (diff) | |
| download | linux-dev-ea426e6c62d0f742d87451adc47e91d87b9c3d27.tar.xz linux-dev-ea426e6c62d0f742d87451adc47e91d87b9c3d27.zip | |
Blackfin: unify cache init functions
The CPLB implementations (mpu/nompu) had exact copies of the cacheinit
code. Even the i/d cache functions are largely the same. So unify them
both in the common kernel cache code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/cache-c.c')
| -rw-r--r-- | arch/blackfin/mach-common/cache-c.c | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index b59ce3cb3807..4ebbd78db3a4 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c @@ -1,14 +1,16 @@ /* * Blackfin cache control code (simpler control-style functions) * - * Copyright 2004-2008 Analog Devices Inc. + * Copyright 2004-2009 Analog Devices Inc. * * Enter bugs at http://blackfin.uclinux.org/ * * Licensed under the GPL-2 or later. */ +#include <linux/init.h> #include <asm/blackfin.h> +#include <asm/cplbinit.h> /* Invalidate the Entire Data cache by * clearing DMC[1:0] bits @@ -34,3 +36,43 @@ void blackfin_invalidate_entire_icache(void) SSYNC(); } +#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) + +static void +bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, + unsigned long cplb_data, unsigned long mem_control, + unsigned long mem_mask) +{ + int i; + + for (i = 0; i < MAX_CPLBS; i++) { + bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); + bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); + } + + _enable_cplb(mem_control, mem_mask); +} + +#ifdef CONFIG_BFIN_ICACHE +void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) +{ + bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, + (IMC | ENICPLB)); +} +#endif + +#ifdef CONFIG_BFIN_DCACHE +void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) +{ + /* + * Anomaly notes: + * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL + * register, so that the port preferences for DAG0 and DAG1 are set + * to port B + */ + bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, + (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); +} +#endif + +#endif |