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| author |   Jesper Nilsson <jesper@jni.nu> | 2018-03-11 11:05:23 +0100 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:56:05 +0100 |
| commit | c690eddc2f3b44b24520f4a77cc3a4c9bde7d571 (patch) | |
| tree | b7ba2caa6ebb2e36a529f9bf7182c9e0a73d53c4 /arch/cris/include/asm/cacheflush.h | |
| parent | arch: remove tile port (diff) | |
| download | linux-dev-c690eddc2f3b44b24520f4a77cc3a4c9bde7d571.tar.xz linux-dev-c690eddc2f3b44b24520f4a77cc3a4c9bde7d571.zip | |
CRIS: Drop support for the CRIS port
The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)
The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.
Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.
So long and thanks for all the fish!
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/cris/include/asm/cacheflush.h')
| -rw-r--r-- | arch/cris/include/asm/cacheflush.h | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/arch/cris/include/asm/cacheflush.h b/arch/cris/include/asm/cacheflush.h deleted file mode 100644 index 0da1c76a2bbc..000000000000 --- a/arch/cris/include/asm/cacheflush.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_CACHEFLUSH_H -#define _CRIS_CACHEFLUSH_H - -/* Keep includes the same across arches. */ -#include <linux/mm.h> - -/* The cache doesn't need to be flushed when TLB entries change because - * the cache is mapped to physical memory, not virtual memory - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -int change_page_attr(struct page *page, int numpages, pgprot_t prot); - -#endif /* _CRIS_CACHEFLUSH_H */ |