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| author |   Jesper Nilsson <jesper@jni.nu> | 2018-03-11 11:05:23 +0100 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:56:05 +0100 |
| commit | c690eddc2f3b44b24520f4a77cc3a4c9bde7d571 (patch) | |
| tree | b7ba2caa6ebb2e36a529f9bf7182c9e0a73d53c4 /arch/cris/include/uapi | |
| parent | arch: remove tile port (diff) | |
| download | linux-dev-c690eddc2f3b44b24520f4a77cc3a4c9bde7d571.tar.xz linux-dev-c690eddc2f3b44b24520f4a77cc3a4c9bde7d571.zip | |
CRIS: Drop support for the CRIS port
The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)
The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.
Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.
So long and thanks for all the fish!
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/cris/include/uapi')
29 files changed, 0 insertions, 9447 deletions
diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh deleted file mode 100644 index 6ac3a7bc9760..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh +++ /dev/null @@ -1,7306 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 1 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 0 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h deleted file mode 100644 index 2644bcbe4490..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backward compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile u32*)(reg)) -#define IO_RD_B(reg) (*(volatile u8*)(reg)) -#define IO_RD_W(reg) (*(volatile u16*)(reg)) -#define IO_RD_D(reg) (*(volatile u32*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile u32*) -# define IO_TYPECAST_RO_UDWORD (const volatile u32*) -# define IO_TYPECAST_UWORD (volatile u16*) -# define IO_TYPECAST_RO_UWORD (const volatile u16*) -# define IO_TYPECAST_BYTE (volatile u8*) -# define IO_TYPECAST_RO_BYTE (const volatile u8*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include <arch/sv_addr.agh> - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/arch/cris/include/uapi/arch-v10/arch/svinto.h b/arch/cris/include/uapi/arch-v10/arch/svinto.h deleted file mode 100644 index 793a4275d26a..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/svinto.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_SVINTO_H -#define _ASM_CRIS_SVINTO_H - -#include <arch/sv_addr_ag.h> - -extern unsigned int genconfig_shadow; /* defined and set in head.S */ - -/* dma stuff */ - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; - -/* Do remember that DMA does not go through the MMU and needs - * a real physical address, not an address virtually mapped or - * paged. Therefore the buf/next ptrs below are unsigned long instead - * of void * to give a warning if you try to put a pointer directly - * to them instead of going through virt_to_phys/phys_to_virt. - */ - -typedef struct etrax_dma_descr { - unsigned short sw_len; /* 0-1 */ - unsigned short ctrl; /* 2-3 */ - unsigned long next; /* 4-7 */ - unsigned long buf; /* 8-11 */ - unsigned short hw_len; /* 12-13 */ - unsigned char status; /* 14 */ - unsigned char fifo_len; /* 15 */ -} etrax_dma_descr; - - -/* Use this for constant numbers only */ -#define RESET_DMA_NUM( n ) \ - *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) - -/* Use this for constant numbers or symbols, - * having two macros makes it possible to use constant expressions. - */ -#define RESET_DMA( n ) RESET_DMA_NUM( n ) - - -/* Use this for constant numbers only */ -#define WAIT_DMA_NUM( n ) \ - while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ - IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) - -/* Use this for constant numbers or symbols - * having two macros makes it possible to use constant expressions. - */ -#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) - -extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); -extern void flush_etrax_cache(void); - -#endif diff --git a/arch/cris/include/uapi/arch-v10/arch/user.h b/arch/cris/include/uapi/arch-v10/arch/user.h deleted file mode 100644 index 5b9288527b98..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/user.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASM_CRIS_ARCH_USER_H -#define __ASM_CRIS_ARCH_USER_H - -/* User mode registers, used for core dumps. In order to keep ELF_NGREG - sensible we let all registers be 32 bits. The csr registers are included - for future use. */ -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* Stack pointer. */ - unsigned long pc; /* Program counter. */ - unsigned long p0; /* Constant zero (only 8 bits). */ - unsigned long vr; /* Version register (only 8 bits). */ - unsigned long p2; /* Reserved. */ - unsigned long p3; /* Reserved. */ - unsigned long p4; /* Constant zero (only 16 bits). */ - unsigned long ccr; /* Condition code register (only 16 bits). */ - unsigned long p6; /* Reserved. */ - unsigned long mof; /* Multiply overflow register. */ - unsigned long p8; /* Constant zero. */ - unsigned long ibr; /* Not accessible. */ - unsigned long irp; /* Not accessible. */ - unsigned long srp; /* Subroutine return pointer. */ - unsigned long bar; /* Not accessible. */ - unsigned long dccr; /* Dword condition code register. */ - unsigned long brp; /* Not accessible. */ - unsigned long usp; /* User-mode stack pointer. Same as sp when - in user mode. */ - unsigned long csrinstr; /* Internal status registers. */ - unsigned long csraddr; - unsigned long csrdata; -}; - -#endif diff --git a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h deleted file mode 100644 index 1072d5bf7d4f..000000000000 --- a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ - -#ifndef _UAPICRYPTOCOP_H -#define _UAPICRYPTOCOP_H - -#include <linux/uio.h> - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; - - - - -#endif /* _UAPICRYPTOCOP_H */ diff --git a/arch/cris/include/uapi/arch-v32/arch/user.h b/arch/cris/include/uapi/arch-v32/arch/user.h deleted file mode 100644 index 3576b540ba78..000000000000 --- a/arch/cris/include/uapi/arch-v32/arch/user.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild deleted file mode 100644 index 3470c6e9c7b9..000000000000 --- a/arch/cris/include/uapi/asm/Kbuild +++ /dev/null @@ -1,22 +0,0 @@ -# UAPI Header export list -include include/uapi/asm-generic/Kbuild.asm - -generic-y += auxvec.h -generic-y += bitsperlong.h -generic-y += bpf_perf_event.h -generic-y += errno.h -generic-y += fcntl.h -generic-y += ioctl.h -generic-y += ipcbuf.h -generic-y += kvm_para.h -generic-y += mman.h -generic-y += msgbuf.h -generic-y += poll.h -generic-y += resource.h -generic-y += sembuf.h -generic-y += shmbuf.h -generic-y += siginfo.h -generic-y += socket.h -generic-y += sockios.h -generic-y += statfs.h -generic-y += types.h diff --git a/arch/cris/include/uapi/asm/byteorder.h b/arch/cris/include/uapi/asm/byteorder.h deleted file mode 100644 index 6e19891e06ee..000000000000 --- a/arch/cris/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_BYTEORDER_H -#define _CRIS_BYTEORDER_H - -#include <linux/byteorder/little_endian.h> - -#endif - - diff --git a/arch/cris/include/uapi/asm/elf.h b/arch/cris/include/uapi/asm/elf.h deleted file mode 100644 index ea4cbdafe885..000000000000 --- a/arch/cris/include/uapi/asm/elf.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASMCRIS_ELF_H -#define __ASMCRIS_ELF_H - -/* - * ELF register definitions.. - */ - -#ifdef __arch_v32 -#include <asm/elf_v32.h> -#else -#include <asm/elf_v10.h> -#endif - -#define R_CRIS_NONE 0 -#define R_CRIS_8 1 -#define R_CRIS_16 2 -#define R_CRIS_32 3 -#define R_CRIS_8_PCREL 4 -#define R_CRIS_16_PCREL 5 -#define R_CRIS_32_PCREL 6 -#define R_CRIS_GNU_VTINHERIT 7 -#define R_CRIS_GNU_VTENTRY 8 -#define R_CRIS_COPY 9 -#define R_CRIS_GLOB_DAT 10 -#define R_CRIS_JUMP_SLOT 11 -#define R_CRIS_RELATIVE 12 -#define R_CRIS_16_GOT 13 -#define R_CRIS_32_GOT 14 -#define R_CRIS_16_GOTPLT 15 -#define R_CRIS_32_GOTPLT 16 -#define R_CRIS_32_GOTREL 17 -#define R_CRIS_32_PLT_GOTREL 18 -#define R_CRIS_32_PLT_PCREL 19 - -typedef unsigned long elf_greg_t; - -/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is - thus exposed to user-space. */ -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* A placeholder; CRIS does not have any fp regs. */ -typedef unsigned long elf_fpregset_t; - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_CRIS - -/* The master for these definitions is {binutils}/include/elf/cris.h: */ -/* User symbols in this file have a leading underscore. */ -#define EF_CRIS_UNDERSCORE 0x00000001 - -/* This is a mask for different incompatible machine variants. */ -#define EF_CRIS_VARIANT_MASK 0x0000000e - -/* Variant 0; may contain v0..10 object. */ -#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 - -/* Variant 1; contains v32 object. */ -#define EF_CRIS_VARIANT_V32 0x00000002 - -/* Variant 2; contains object compatible with v32 and v10. */ -#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 -/* End of excerpt from {binutils}/include/elf/cris.h. */ - -#define ELF_EXEC_PAGESIZE 8192 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) - -/* This yields a mask that user programs can use to figure out what - instruction set this CPU supports. This could be done in user space, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. -*/ - -#define ELF_PLATFORM (NULL) - -#endif diff --git a/arch/cris/include/uapi/asm/elf_v10.h b/arch/cris/include/uapi/asm/elf_v10.h deleted file mode 100644 index b1515f2684da..000000000000 --- a/arch/cris/include/uapi/asm/elf_v10.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASMCRIS_ARCH_ELF_H -#define __ASMCRIS_ARCH_ELF_H - -#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 - -/* Matches struct user_regs_struct */ -#define ELF_NGREG 35 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* - * ELF register definitions.. - */ - -#include <asm/ptrace.h> - -/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program - starts (a register; assume first param register for CRIS) - contains a pointer to a function which might be - registered using `atexit'. This provides a mean for the - dynamic linker to call DT_FINI functions for shared libraries - that have been loaded before the code runs. - - A value of 0 tells we have no such handler. */ - -/* Explicitly set registers to 0 to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ -} while (0) - -/* The additional layer below is because the stack pointer is missing in - the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, - and should be filled in according to the layout of the user_regs_struct - struct; regs is a pt_regs struct. We dump all registers, though several are - obviously unnecessary. That way there's less need for intelligence at - the receiving end (i.e. gdb). */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* sp */ \ - pr_reg[15] = regs->irp; /* pc */ \ - pr_reg[16] = 0; /* p0 */ \ - pr_reg[17] = rdvr(); /* vr */ \ - pr_reg[18] = 0; /* p2 */ \ - pr_reg[19] = 0; /* p3 */ \ - pr_reg[20] = 0; /* p4 */ \ - pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ - pr_reg[22] = 0; /* p6 */ \ - pr_reg[23] = regs->mof; /* mof */ \ - pr_reg[24] = 0; /* p8 */ \ - pr_reg[25] = 0; /* ibr */ \ - pr_reg[26] = 0; /* irp */ \ - pr_reg[27] = regs->srp; /* srp */ \ - pr_reg[28] = 0; /* bar */ \ - pr_reg[29] = regs->dccr; /* dccr */ \ - pr_reg[30] = 0; /* brp */ \ - pr_reg[31] = rdusp(); /* usp */ \ - pr_reg[32] = 0; /* csrinstr */ \ - pr_reg[33] = 0; /* csraddr */ \ - pr_reg[34] = 0; /* csrdata */ - - -#endif diff --git a/arch/cris/include/uapi/asm/elf_v32.h b/arch/cris/include/uapi/asm/elf_v32.h deleted file mode 100644 index cc00ffdb7f9c..000000000000 --- a/arch/cris/include/uapi/asm/elf_v32.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_ELF_H -#define _ASM_CRIS_ELF_H - -#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 - -/* Matches struct user_regs_struct */ -#define ELF_NGREG 32 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* CRISv32 ELF register definitions. */ - -#include <asm/ptrace.h> - -/* Explicitly zero out registers to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ - (_r)->acr = 0; \ -} while (0) - -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. - */ -#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) - -/* - * This is basically a pt_regs with the additional definition - * of the stack pointer since it's needed in a core dump. - * pr_regs is a elf_gregset_t and should be filled according - * to the layout of user_regs_struct. - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* SP */ \ - pr_reg[15] = regs->acr; /* ACR */ \ - pr_reg[16] = 0; /* BZ */ \ - pr_reg[17] = rdvr(); /* VR */ \ - pr_reg[18] = 0; /* PID */ \ - pr_reg[19] = regs->srs; /* SRS */ \ - pr_reg[20] = 0; /* WZ */ \ - pr_reg[21] = regs->exs; /* EXS */ \ - pr_reg[22] = regs->eda; /* EDA */ \ - pr_reg[23] = regs->mof; /* MOF */ \ - pr_reg[24] = 0; /* DZ */ \ - pr_reg[25] = 0; /* EBP */ \ - pr_reg[26] = regs->erp; /* ERP */ \ - pr_reg[27] = regs->srp; /* SRP */ \ - pr_reg[28] = 0; /* NRP */ \ - pr_reg[29] = regs->ccs; /* CCS */ \ - pr_reg[30] = rdusp(); /* USP */ \ - pr_reg[31] = regs->spc; /* SPC */ \ - -#endif /* _ASM_CRIS_ELF_H */ diff --git a/arch/cris/include/uapi/asm/ethernet.h b/arch/cris/include/uapi/asm/ethernet.h deleted file mode 100644 index e0c1a6322824..000000000000 --- a/arch/cris/include/uapi/asm/ethernet.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * ioctl defines for ethernet driver - * - * Copyright (c) 2001 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef _CRIS_ETHERNET_H -#define _CRIS_ETHERNET_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ -#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ -#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ -#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 -#endif /* _CRIS_ETHERNET_H */ diff --git a/arch/cris/include/uapi/asm/etraxgpio.h b/arch/cris/include/uapi/asm/etraxgpio.h deleted file mode 100644 index 10ab0dd45bfe..000000000000 --- a/arch/cris/include/uapi/asm/etraxgpio.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * The following devices are accessible using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers. - * - * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/gpiog minor 3 - * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - * g1-g7 and g25-g31 is both input and outputs but on different pins - * Also note that some bits change pins depending on what interfaces - * are enabled. - */ -#ifndef _ASM_ETRAXGPIO_H -#define _ASM_ETRAXGPIO_H - -#define GPIO_MINOR_FIRST 0 - -#define ETRAXGPIO_IOCTYPE 43 - -/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_G 3 -#define GPIO_MINOR_LAST 3 -#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST - - -/* supported ioctl _IOC_NR's */ - -#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ -#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ -#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ - -/* the alarm is waited for by select() */ - -#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ -#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ -#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ - -/* LED ioctl */ -#define IO_LEDACTIVE_SET 0x7 /* set active led - * 0=off, 1=green, 2=red, 3=yellow */ - -/* GPIO direction ioctl's */ -#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, - returns mask with current inputs (obsolete) */ -#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, - returns mask with current outputs (obsolete)*/ - -/* LED ioctl extended */ -#define IO_LED_SETBIT 0xB -#define IO_LED_CLRBIT 0xC - -/* SHUTDOWN ioctl */ -#define IO_SHUTDOWN 0xD -#define IO_GET_PWR_BT 0xE - -/* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) - msb, data_mask[7:0] , clk_mask[7:0] - */ -#define IO_CFG_WRITE_MODE 0xF -#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) - -/* The following 4 ioctl's take a pointer as argument and handles - * 32 bit ports (port G) properly. - * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT - */ -#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ -#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ -#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ - /* *arg updated with current input pins. */ -#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ - /* *arg updated with current output pins. */ - -#endif diff --git a/arch/cris/include/uapi/asm/ioctls.h b/arch/cris/include/uapi/asm/ioctls.h deleted file mode 100644 index 92d654ce3d84..000000000000 --- a/arch/cris/include/uapi/asm/ioctls.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ARCH_CRIS_IOCTLS_H__ -#define __ARCH_CRIS_IOCTLS_H__ - -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ -#define TIOCSERWRRS485 0x5462 /* write rs-485 */ -#define TIOCSRS485 0x5463 /* enable rs-485 */ - -#include <asm-generic/ioctls.h> - -#endif diff --git a/arch/cris/include/uapi/asm/param.h b/arch/cris/include/uapi/asm/param.h deleted file mode 100644 index ae296115c7c9..000000000000 --- a/arch/cris/include/uapi/asm/param.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASMCRIS_PARAM_H -#define _ASMCRIS_PARAM_H - -/* Currently we assume that HZ=100 is good for CRIS. */ - -#define EXEC_PAGESIZE 8192 - -#include <asm-generic/param.h> - -#endif /* _ASMCRIS_PARAM_H */ diff --git a/arch/cris/include/uapi/asm/posix_types.h b/arch/cris/include/uapi/asm/posix_types.h deleted file mode 100644 index c75d8b0acc99..000000000000 --- a/arch/cris/include/uapi/asm/posix_types.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ -/* I guess we should write these in assembler because they are used often. */ - -#ifndef __ARCH_CRIS_POSIX_TYPES_H -#define __ARCH_CRIS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned short __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -#define __kernel_uid_t __kernel_uid_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include <asm-generic/posix_types.h> - -#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/arch/cris/include/uapi/asm/ptrace.h b/arch/cris/include/uapi/asm/ptrace.h deleted file mode 100644 index 99de59e54613..000000000000 --- a/arch/cris/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifdef __arch_v32 -#include <asm/ptrace_v32.h> -#else -#include <asm/ptrace_v10.h> -#endif diff --git a/arch/cris/include/uapi/asm/ptrace_v10.h b/arch/cris/include/uapi/asm/ptrace_v10.h deleted file mode 100644 index 4ffffb7ab102..000000000000 --- a/arch/cris/include/uapi/asm/ptrace_v10.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Frame types */ - -#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ -#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return - path */ - -/* Register numbers in the ptrace system call interface */ - -#define PT_FRAMETYPE 0 -#define PT_ORIG_R10 1 -#define PT_R13 2 -#define PT_R12 3 -#define PT_R11 4 -#define PT_R10 5 -#define PT_R9 6 -#define PT_R8 7 -#define PT_R7 8 -#define PT_R6 9 -#define PT_R5 10 -#define PT_R4 11 -#define PT_R3 12 -#define PT_R2 13 -#define PT_R1 14 -#define PT_R0 15 -#define PT_MOF 16 -#define PT_DCCR 17 -#define PT_SRP 18 -#define PT_IRP 19 /* This is actually the debugged process' PC */ -#define PT_CSRINSTR 20 /* CPU Status record remnants - - valid if frametype == busfault */ -#define PT_CSRADDR 21 -#define PT_CSRDATA 22 -#define PT_USP 23 /* special case - USP is not in the pt_regs */ -#define PT_MAX 23 - -/* Condition code bit numbers. The same numbers apply to CCR of course, - but we use DCCR everywhere else, so let's try and be consistent. */ -#define C_DCCR_BITNR 0 -#define V_DCCR_BITNR 1 -#define Z_DCCR_BITNR 2 -#define N_DCCR_BITNR 3 -#define X_DCCR_BITNR 4 -#define I_DCCR_BITNR 5 -#define B_DCCR_BITNR 6 -#define M_DCCR_BITNR 7 -#define U_DCCR_BITNR 8 -#define P_DCCR_BITNR 9 -#define F_DCCR_BITNR 10 - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long frametype; /* type of stackframe */ - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ - unsigned long r13; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long mof; - unsigned long dccr; - unsigned long srp; - unsigned long irp; /* This is actually the debugged process' PC */ - unsigned long csrinstr; - unsigned long csraddr; - unsigned long csrdata; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -/* bit 8 is user-mode flag */ -#define user_mode(regs) (((regs)->dccr & 0x100) != 0) -#define instruction_pointer(regs) ((regs)->irp) -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/cris/include/uapi/asm/ptrace_v32.h b/arch/cris/include/uapi/asm/ptrace_v32.h deleted file mode 100644 index a91c4aacb14f..000000000000 --- a/arch/cris/include/uapi/asm/ptrace_v32.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Register numbers in the ptrace system call interface */ - -#define PT_ORIG_R10 0 -#define PT_R0 1 -#define PT_R1 2 -#define PT_R2 3 -#define PT_R3 4 -#define PT_R4 5 -#define PT_R5 6 -#define PT_R6 7 -#define PT_R7 8 -#define PT_R8 9 -#define PT_R9 10 -#define PT_R10 11 -#define PT_R11 12 -#define PT_R12 13 -#define PT_R13 14 -#define PT_ACR 15 -#define PT_SRS 16 -#define PT_MOF 17 -#define PT_SPC 18 -#define PT_CCS 19 -#define PT_SRP 20 -#define PT_ERP 21 /* This is actually the debugged process' PC */ -#define PT_EXS 22 -#define PT_EDA 23 -#define PT_USP 24 /* special case - USP is not in the pt_regs */ -#define PT_PPC 25 /* special case - pseudo PC */ -#define PT_BP 26 /* Base number for BP registers. */ -#define PT_BP_CTRL 26 /* BP control register. */ -#define PT_MAX 40 - -/* Condition code bit numbers. */ -#define C_CCS_BITNR 0 -#define V_CCS_BITNR 1 -#define Z_CCS_BITNR 2 -#define N_CCS_BITNR 3 -#define X_CCS_BITNR 4 -#define I_CCS_BITNR 5 -#define U_CCS_BITNR 6 -#define P_CCS_BITNR 7 -#define R_CCS_BITNR 8 -#define S_CCS_BITNR 9 -#define M_CCS_BITNR 30 -#define Q_CCS_BITNR 31 -#define CCS_SHIFT 10 /* Shift count for each level in CCS */ - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL. */ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long acr; - unsigned long srs; - unsigned long mof; - unsigned long spc; - unsigned long ccs; - unsigned long srp; - unsigned long erp; /* This is actually the debugged process' PC */ - /* For debugging purposes; saved only when needed. */ - unsigned long exs; - unsigned long eda; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -#define arch_has_single_step() (1) -#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) -#define instruction_pointer(regs) ((regs)->erp) -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/cris/include/uapi/asm/rs485.h b/arch/cris/include/uapi/asm/rs485.h deleted file mode 100644 index 041d31fa33d5..000000000000 --- a/arch/cris/include/uapi/asm/rs485.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* RS-485 structures */ - -/* Used with ioctl() TIOCSERSETRS485 for backward compatibility! - * XXX: Do not use it for new code! - */ -struct rs485_control { - unsigned short rts_on_send; - unsigned short rts_after_sent; - unsigned long delay_rts_before_send; - unsigned short enabled; -}; - -/* Used with ioctl() TIOCSERWRRS485 */ -struct rs485_write { - unsigned short outc_size; - unsigned char *outc; -}; - diff --git a/arch/cris/include/uapi/asm/setup.h b/arch/cris/include/uapi/asm/setup.h deleted file mode 100644 index 4854ace9db76..000000000000 --- a/arch/cris/include/uapi/asm/setup.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_SETUP_H -#define _CRIS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#endif diff --git a/arch/cris/include/uapi/asm/sigcontext.h b/arch/cris/include/uapi/asm/sigcontext.h deleted file mode 100644 index 97565ce3f0b9..000000000000 --- a/arch/cris/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef _ASM_CRIS_SIGCONTEXT_H -#define _ASM_CRIS_SIGCONTEXT_H - -#include <asm/ptrace.h> - -/* This struct is saved by setup_frame in signal.c, to keep the current context while - a signal handler is executed. It's restored by sys_sigreturn. - - To keep things simple, we use pt_regs here even though normally you just specify - the list of regs to save. Then we can use copy_from_user on the entire regs instead - of a bunch of get_user's as well... - -*/ - -struct sigcontext { - struct pt_regs regs; /* needs to be first */ - unsigned long oldmask; - unsigned long usp; /* usp before stacking this gunk on it */ -}; - -#endif - diff --git a/arch/cris/include/uapi/asm/signal.h b/arch/cris/include/uapi/asm/signal.h deleted file mode 100644 index e4ab00f00111..000000000000 --- a/arch/cris/include/uapi/asm/signal.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_CRIS_SIGNAL_H -#define _UAPI_ASM_CRIS_SIGNAL_H - -#include <linux/types.h> - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include <asm-generic/signal-defs.h> - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - - -#endif /* _UAPI_ASM_CRIS_SIGNAL_H */ diff --git a/arch/cris/include/uapi/asm/stat.h b/arch/cris/include/uapi/asm/stat.h deleted file mode 100644 index cdb74d5862e4..000000000000 --- a/arch/cris/include/uapi/asm/stat.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_STAT_H -#define _CRIS_STAT_H - -/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in - the kernel if necessary. */ - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -#define STAT_HAVE_NSEC 1 - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ - - unsigned long long st_ino; -}; - -#endif diff --git a/arch/cris/include/uapi/asm/swab.h b/arch/cris/include/uapi/asm/swab.h deleted file mode 100644 index 4adf1e9f0b09..000000000000 --- a/arch/cris/include/uapi/asm/swab.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * CRIS byte swapping. - */ diff --git a/arch/cris/include/uapi/asm/sync_serial.h b/arch/cris/include/uapi/asm/sync_serial.h deleted file mode 100644 index f2d468889ba9..000000000000 --- a/arch/cris/include/uapi/asm/sync_serial.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include <linux/ioctl.h> - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) -#define SSP_INPUT _IOR('S', 7, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 -#define CODEC_f32768 16 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 -/* FREQ_* with values where bit (value & 0x10) is set are */ -/* used for CODEC_f32768 */ -#define FREQ_4096kHz 16 /* CODEC_f32768 */ - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \ - ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \ - (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 -#define SECOND_WORD_SYNC 0x40000 -#define LATE_SYNC 0x80000 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -/* To ensure that the timestamps are aligned with the data being read - * the read length MUST be a multiple of the length of the DMA buffers. - * - * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below. - */ -#define SSP_INPUT_CHUNK_SIZE 256 - -/* Request struct to pass through the ioctl interface to read - * data with timestamps. - */ -struct ssp_request { - char __user *buf; /* Where to put the data. */ - size_t len; /* Size of buf. MUST be a multiple of */ - /* SSP_INPUT_CHUNK_SIZE! */ - struct timespec ts; /* The time the data was sampled. */ -}; - -#endif diff --git a/arch/cris/include/uapi/asm/termbits.h b/arch/cris/include/uapi/asm/termbits.h deleted file mode 100644 index 86925dc1fcae..000000000000 --- a/arch/cris/include/uapi/asm/termbits.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef __ARCH_ETRAX100_TERMBITS_H__ -#define __ARCH_ETRAX100_TERMBITS_H__ - -#include <linux/posix_types.h> - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -/* - * 3 2 1 - * 10 987 654 321 098 765 432 109 876 543 210 - * | | ||| CBAUD - * obaud - * - * ||CSIZE - * - * |CSTOP - * |CREAD - * |CPARENB - * - * |CPARODD - * |HUPCL - * |CLOCAL - * |CBAUDEX - * 10 987 654 321 098 765 432 109 876 543 210 - * | || || CIBAUD, IBSHIFT=16 - * ibaud - * |CMSPAR - * | CRTSCTS - * x x xxx xxx x x xx Free bits - */ - -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 - -/* Unsupported rates, but needed to avoid compile error. */ -#define B500000 0010005 -#define B576000 0010006 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 - -/* etrax supports these additional three baud rates */ -#define B921600 0010005 -#define B1843200 0010006 -#define B6250000 0010007 -/* ETRAX FS supports this as well */ -#define B12500000 0010010 -#define CIBAUD 002003600000 /* input baud rate (used in v32) */ -/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX - * shifted left IBSHIFT bits. - */ -#define IBSHIFT 16 -#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 -#define EXTPROC 0200000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif diff --git a/arch/cris/include/uapi/asm/termios.h b/arch/cris/include/uapi/asm/termios.h deleted file mode 100644 index d87800a6d854..000000000000 --- a/arch/cris/include/uapi/asm/termios.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_CRIS_TERMIOS_H -#define _UAPI_CRIS_TERMIOS_H - -#include <asm/termbits.h> -#include <asm/ioctls.h> -#include <asm/rs485.h> -#include <linux/serial.h> - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - - -#endif /* _UAPI_CRIS_TERMIOS_H */ diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h deleted file mode 100644 index 7aba513b082d..000000000000 --- a/arch/cris/include/uapi/asm/unistd.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_CRIS_UNISTD_H_ -#define _UAPI_ASM_CRIS_UNISTD_H_ - -/* - * This file contains the system call numbers, and stub macros for libc. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 -/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 -#define __NR_migrate_pages 294 -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 -#define __NR_set_robust_list 311 -#define __NR_get_robust_list 312 -#define __NR_splice 313 -#define __NR_sync_file_range 314 -#define __NR_tee 315 -#define __NR_vmsplice 316 -#define __NR_move_pages 317 -#define __NR_getcpu 318 -#define __NR_epoll_pwait 319 -#define __NR_utimensat 320 -#define __NR_signalfd 321 -#define __NR_timerfd_create 322 -#define __NR_eventfd 323 -#define __NR_fallocate 324 -#define __NR_timerfd_settime 325 -#define __NR_timerfd_gettime 326 -#define __NR_signalfd4 327 -#define __NR_eventfd2 328 -#define __NR_epoll_create1 329 -#define __NR_dup3 330 -#define __NR_pipe2 331 -#define __NR_inotify_init1 332 -#define __NR_preadv 333 -#define __NR_pwritev 334 -#define __NR_setns 335 -#define __NR_name_to_handle_at 336 -#define __NR_open_by_handle_at 337 -#define __NR_rt_tgsigqueueinfo 338 -#define __NR_perf_event_open 339 -#define __NR_recvmmsg 340 -#define __NR_accept4 341 -#define __NR_fanotify_init 342 -#define __NR_fanotify_mark 343 -#define __NR_prlimit64 344 -#define __NR_clock_adjtime 345 -#define __NR_syncfs 346 -#define __NR_sendmmsg 347 -#define __NR_process_vm_readv 348 -#define __NR_process_vm_writev 349 -#define __NR_kcmp 350 -#define __NR_finit_module 351 -#define __NR_sched_setattr 352 -#define __NR_sched_getattr 353 -#define __NR_renameat2 354 -#define __NR_seccomp 355 -#define __NR_getrandom 356 -#define __NR_memfd_create 357 -#define __NR_bpf 358 -#define __NR_execveat 359 - -#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */ |