diff options
| author |   Guo Ren <ren_guo@c-sky.com> | 2019-06-18 17:20:10 +0800 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2019-07-19 14:21:36 +0800 |
| commit | 9d35dc3006a9865eb5b55cc79df49933601131f8 (patch) | |
| tree | 6f16dbd7f5111bcea394079e199bb68701459235 /arch/csky/include/asm/pgtable.h | |
| parent | dt-bindings: csky: Add csky PMU bindings (diff) | |
| download | linux-dev-9d35dc3006a9865eb5b55cc79df49933601131f8.tar.xz linux-dev-9d35dc3006a9865eb5b55cc79df49933601131f8.zip | |
csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/include/asm/pgtable.h')
| -rw-r--r-- | arch/csky/include/asm/pgtable.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h index dcea277c09ae..c429a6f347de 100644 --- a/arch/csky/include/asm/pgtable.h +++ b/arch/csky/include/asm/pgtable.h @@ -290,8 +290,6 @@ static inline pte_t *pte_offset(pmd_t *dir, unsigned long address) extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); -extern void show_jtlb_table(void); - void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *pte); |