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| author |   Guo Ren <ren_guo@c-sky.com> | 2018-09-05 14:25:12 +0800 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2018-10-25 23:36:19 +0800 |
| commit | 013de2d6671d89de3397904749c86a69ac0686f7 (patch) | |
| tree | a957e4719ccb7f7383bfa17f8937d61409ee9119 /arch/csky/include/uapi/asm/sigcontext.h | |
| parent | csky: Cache and TLB routines (diff) | |
| download | linux-dev-013de2d6671d89de3397904749c86a69ac0686f7.tar.xz linux-dev-013de2d6671d89de3397904749c86a69ac0686f7.zip | |
csky: MMU and page table management
This patch adds files related to memory management and here is our
memory-layout:
Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB)
Pkmap : 0xff800000 – 0xffc00000 (4 MB)
Vmalloc : 0xf0200000 – 0xff000000 (238 MB)
Lowmem : 0x80000000 – 0xc0000000 (1GB)
abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
abiv2 CPUs are all PIPT cache and they could support highmem.
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
memory page table for it.
Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Christoph Hellwig <hch@infradead.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/include/uapi/asm/sigcontext.h')
0 files changed, 0 insertions, 0 deletions