diff options
| author |   Andreas Herrmann <andreas.herrmann3@amd.com> | 2007-02-13 13:26:23 +0100 |
|---|---|---|
| committer |   Andi Kleen <andi@basil.nowhere.org> | 2007-02-13 13:26:23 +0100 |
| commit | 6c5806cae50717f31878d0da29109b10610ab862 (patch) | |
| tree | 65dd7caf0b0767ccc5ac5d27c992bce00da8f353 /arch/i386/kernel/cpu/mtrr/main.c | |
| parent | [PATCH] i386: Convert /proc/apm to seqfile (diff) | |
| download | linux-dev-6c5806cae50717f31878d0da29109b10610ab862.tar.xz linux-dev-6c5806cae50717f31878d0da29109b10610ab862.zip | |
[PATCH] i386: fix size_or_mask and size_and_mask
mtrr: fix size_or_mask and size_and_mask
This fixes two bugs in /proc/mtrr interface:
o If physical address size crosses the 44 bit boundary
size_or_mask is evaluated wrong.
o size_and_mask limits width of physical base
address for an MTRR to be less than 44 bits.
TBD: later patch had one more change, but I think that was bogus.
TBD: need to double check
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'arch/i386/kernel/cpu/mtrr/main.c')
| -rw-r--r-- | arch/i386/kernel/cpu/mtrr/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/i386/kernel/cpu/mtrr/main.c b/arch/i386/kernel/cpu/mtrr/main.c index 16bb7ea87145..0acfb6a5a220 100644 --- a/arch/i386/kernel/cpu/mtrr/main.c +++ b/arch/i386/kernel/cpu/mtrr/main.c @@ -50,7 +50,7 @@ u32 num_var_ranges = 0; unsigned int *usage_table; static DEFINE_MUTEX(mtrr_mutex); -u32 size_or_mask, size_and_mask; +u64 size_or_mask, size_and_mask; static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; @@ -662,8 +662,8 @@ void __init mtrr_bp_init(void) boot_cpu_data.x86_mask == 0x4)) phys_addr = 36; - size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1); - size_and_mask = ~size_or_mask & 0xfff00000; + size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); + size_and_mask = ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 6) { /* VIA C* family have Intel style MTRRs, but |