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authorRobin Holt <holt@sgi.com>2006-11-14 20:50:59 -0600
committerTony Luck <tony.luck@intel.com>2006-11-15 10:12:15 -0800
commitcbf093e8c7447a202e376199cc017161262bd7cd (patch)
tree02d468ac29306ea21c01f0bf16246e7d195ef39c /arch/ia64/kernel/irq.c
parent[PATCH] Use delayed disable mode of ioapic edge triggered interrupts (diff)
downloadlinux-dev-cbf093e8c7447a202e376199cc017161262bd7cd.tar.xz
linux-dev-cbf093e8c7447a202e376199cc017161262bd7cd.zip
[IA64] bte_unaligned_copy() transfers one extra cache line.
When called to do a transfer that has a start offset within the cache line which is uneven between source and destination and a length which terminates the source of the copy exactly on a cache line, one extra line gets copied into a temporary buffer. This is normally not an issue since the buffer is a kernel buffer and only the requested information gets copied into the user buffer. The problem arises when the source ends at the very last physical page of memory. That last cache line does not exist and results in the SHUB chip raising an MCA. Signed-off-by: Robin Holt <holt@sgi.com> Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/irq.c')
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