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| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-02 20:00:54 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-02 20:00:54 -0700 |
| commit | b55a0ff8df92646696c858a8fea4dbf38509f202 (patch) | |
| tree | 9b3fb1da94093e5147b1ef5bcd5277f9187c32cd /arch/m68k/include/asm/m54xxsim.h | |
| parent | Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next (diff) | |
| parent | m68knommu: Implement gpio support for m54xx. (diff) | |
| download | linux-dev-b55a0ff8df92646696c858a8fea4dbf38509f202.tar.xz linux-dev-b55a0ff8df92646696c858a8fea4dbf38509f202.zip | |
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu into next
Pull m68knommu updates from Greg Ungerer:
"Nothing too big, just a handfull of small changes.
A couple of dragonball fixes, coldfire qspi cleanup and fixes, and
some coldfire gpio cleanup, fixes and extensions"
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
m68knommu: Implement gpio support for m54xx.
m68knommu: Make everything thats not exported, static.
m68knommu: setting the gpio data direction register to output doesn't dependent upon the value to output!
m68knommu: add to_irq function so we can map gpios to external interrupts.
m68knommu: qspi declutter.
m68knommu: Fix the 5249/525x qspi base address.
m68knommu: Add qspi clk for Coldfire SoCs without real clks.
m68k: fix a compiler warning when building for DragonBall
m68knommu: Fix mach_sched_init for EZ and VZ DragonBall chips
Diffstat (limited to 'arch/m68k/include/asm/m54xxsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxsim.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index d3bd83887429..a5fbd17ab0a5 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -55,9 +55,15 @@ /* * Generic GPIO support */ -#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ -#define MCFGPIO_IRQ_MAX -1 -#define MCFGPIO_IRQ_VECBASE -1 +#define MCFGPIO_PODR (MCF_MBAR + 0xA00) +#define MCFGPIO_PDDR (MCF_MBAR + 0xA10) +#define MCFGPIO_PPDR (MCF_MBAR + 0xA20) +#define MCFGPIO_SETR (MCF_MBAR + 0xA20) +#define MCFGPIO_CLRR (MCF_MBAR + 0xA30) + +#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */ +#define MCFGPIO_IRQ_MAX 8 +#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE /* * EDGE Port support. |