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author | Jeff Garzik <jeff@garzik.org> | 2012-07-25 15:58:48 -0400 |
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committer | Jeff Garzik <jgarzik@redhat.com> | 2012-07-25 15:58:48 -0400 |
commit | 8407884dd9164ec18ed2afc00f56b87e36c51fcf (patch) | |
tree | b6ea42c231d7d39f454de28a068d78ce11709770 /arch/m68k/platform/coldfire/m525x.c | |
parent | sata_dwc_460ex: device tree may specify dma_channel (diff) | |
parent | Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi (diff) | |
download | linux-dev-8407884dd9164ec18ed2afc00f56b87e36c51fcf.tar.xz linux-dev-8407884dd9164ec18ed2afc00f56b87e36c51fcf.zip |
Merge branch 'master' [vanilla Linus master] into libata-dev.git/upstream
Two bits were appended to the end of the bitfield
list in struct scsi_device. Resolve that conflict
by including both bits.
Conflicts:
include/scsi/scsi_device.h
Diffstat (limited to 'arch/m68k/platform/coldfire/m525x.c')
-rw-r--r-- | arch/m68k/platform/coldfire/m525x.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c new file mode 100644 index 000000000000..8ce905f9b84f --- /dev/null +++ b/arch/m68k/platform/coldfire/m525x.c @@ -0,0 +1,66 @@ +/***************************************************************************/ + +/* + * 525x.c + * + * Copyright (C) 2012, Steven King <sfking@fdwdc.com> + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <asm/machdep.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> + +/***************************************************************************/ + +static void __init m525x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + /* set the GPIO function for the qspi cs gpios */ + /* FIXME: replace with pinmux/pinctl support */ + u32 f = readl(MCFSIM2_GPIOFUNC); + f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0); + writel(f, MCFSIM2_GPIOFUNC); + + /* QSPI irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCF_MBAR + MCFSIM_QSPIICR); + mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +static void __init m525x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_COLDFIRE) + u32 r; + + /* first I2C controller uses regular irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCF_MBAR + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); + + /* second I2C controller is completely different */ + r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); + r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1); + r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1); + writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); +#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */ +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + + m525x_qspi_init(); + m525x_i2c_init(); +} + +/***************************************************************************/ |