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| author |   Greg Ungerer <gerg@uclinux.org> | 2011-03-05 22:17:17 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-03-15 21:01:53 +1000 |
| commit | 254eef7464f0704290af4b91021f512eb4c98d59 (patch) | |
| tree | 4bc61d36dbb146eed72b166f7f75c06d7384adea /arch/m68knommu/platform | |
| parent | m68knommu: move ColdFire 5249 MBAR2 definition (diff) | |
| download | linux-dev-254eef7464f0704290af4b91021f512eb4c98d59.tar.xz linux-dev-254eef7464f0704290af4b91021f512eb4c98d59.zip | |
m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx
The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.
By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform')
| -rw-r--r-- | arch/m68knommu/platform/coldfire/intc-2.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index 71e07fb69302..ec869c8e8890 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -52,11 +52,10 @@ static void intc_irq_mask(struct irq_data *d) u32 val, imrbit; irq -= MCFINT_VECBASE; - imraddr = MCF_IPSBAR; #ifdef MCFICM_INTC1 - imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else - imraddr += MCFICM_INTC0; + imraddr = MCFICM_INTC0; #endif imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; imrbit = 0x1 << (irq & 0x1f); @@ -75,11 +74,10 @@ static void intc_irq_unmask(struct irq_data *d) u32 val, imrbit; irq -= MCFINT_VECBASE; - intaddr = MCF_IPSBAR; #ifdef MCFICM_INTC1 - intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else - intaddr += MCFICM_INTC0; + intaddr = MCFICM_INTC0; #endif imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); @@ -116,9 +114,9 @@ void __init init_IRQ(void) init_vectors(); /* Mask all interrupt sources */ - __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); + __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); #ifdef MCFICM_INTC1 - __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); + __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); #endif for (irq = 0; (irq < NR_IRQS); irq++) { |