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| author |   Paul Burton <paul.burton@mips.com> | 2019-08-31 15:40:43 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-09-03 14:20:43 +0100 |
| commit | 5474682934753827d61d1226ba74ea75787b923d (patch) | |
| tree | fb4e214cd30494841d865732b936179ea8d0b9c7 /arch/mips/Kconfig | |
| parent | MIPS: PCI: refactor ioc3 special handling (diff) | |
| download | linux-dev-5474682934753827d61d1226ba74ea75787b923d.tar.xz linux-dev-5474682934753827d61d1226ba74ea75787b923d.zip | |
MIPS: Select R3k-style TLB in Kconfig
Currently areas where we need to determine whether the TLB is R3k-style
need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX.
Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above,
allowing us to simplify checks for R3k-style TLBs by only checking for
this new Kconfig option.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31c7044e34e6..3f18aa018a0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1575,6 +1575,7 @@ config CPU_R3000 depends on SYS_HAS_CPU_R3000 select CPU_HAS_WB select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_HIGHMEM help @@ -1590,6 +1591,7 @@ config CPU_TX39XX depends on SYS_HAS_CPU_TX39XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB config CPU_VR41XX bool "R41xx" @@ -2280,6 +2282,9 @@ config CPU_R2300_FPU depends on MIPS_FP_SUPPORT default y if CPU_R3000 || CPU_TX39XX +config CPU_R3K_TLB + bool + config CPU_R4K_FPU bool depends on MIPS_FP_SUPPORT @@ -2287,7 +2292,7 @@ config CPU_R4K_FPU config CPU_R4K_CACHE_TLB bool - default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON) config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" |