diff options
| author |   Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-03-24 23:15:50 +0300 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:26 +0100 |
| commit | 0167509574ef1cdb516906db5e8b6ad5ca64ab61 (patch) | |
| tree | 3047fc8adf04601f529e2d497a36d1a79d4681bc /arch/mips/au1000/common/irq.c | |
| parent | [MIPS] Move arch/mips/philips to arch/mips/nxp (diff) | |
| download | linux-dev-0167509574ef1cdb516906db5e8b6ad5ca64ab61.tar.xz linux-dev-0167509574ef1cdb516906db5e8b6ad5ca64ab61.zip | |
[MIPS] Alchemy: don't unmask timer IRQ early
Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:
- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
ALLINTS macro -- this change is blessed by AMD as I saw it in their own
patch; :-)
- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
no 32 KHz crystal.
Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/common/irq.c')
| -rw-r--r-- | arch/mips/au1000/common/irq.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 3c7714f057ac..5528e1412b50 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -1,7 +1,6 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. <source@mvista.com> * * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) * @@ -591,7 +590,7 @@ void __init arch_init_irq(void) imp++; } - set_c0_status(ALLINTS); + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); /* Board specific IRQ initialization. */ |