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authorArnaldo Carvalho de Melo <acme@redhat.com>2019-11-26 11:06:19 -0300
committerArnaldo Carvalho de Melo <acme@redhat.com>2019-11-26 11:06:19 -0300
commit2ea352d5960ad469f5712cf3e293db97beac4e01 (patch)
treec24ae19073f2884867b310ee193d36a82075b60f /arch/mips/cavium-octeon/setup.c
parentMerge branch 'x86/core' into perf/core, to resolve conflicts and to pick up completed topic tree (diff)
parentMerge tag 'for-linus-5.5-1' of git://github.com/cminyard/linux-ipmi (diff)
downloadlinux-dev-2ea352d5960ad469f5712cf3e293db97beac4e01.tar.xz
linux-dev-2ea352d5960ad469f5712cf3e293db97beac4e01.zip
Merge remote-tracking branch 'torvalds/master' into perf/core
To pick up BPF changes we'll need. Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'arch/mips/cavium-octeon/setup.c')
-rw-r--r--arch/mips/cavium-octeon/setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 95034bf5ca83..1f742c32a883 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -844,7 +844,7 @@ void __init prom_init(void)
* BIST should always be enabled when doing a soft reset. L2
* Cache locking for instance is not cleared unless BIST is
* enabled. Unfortunately due to a chip errata G-200 for
- * Cn38XX and CN31XX, BIST msut be disabled on these parts.
+ * Cn38XX and CN31XX, BIST must be disabled on these parts.
*/
if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
OCTEON_IS_MODEL(OCTEON_CN31XX))