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| author |   David Daney <david.daney@cavium.com> | 2016-02-09 11:00:12 -0800 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 14:01:41 +0200 |
| commit | c6d2b22eb5211e96e932428bc1183c6ad57d5e54 (patch) | |
| tree | 9f0fba6e78f38b3a4bcc02be2690818374b301b0 /arch/mips/cavium-octeon/setup.c | |
| parent | MIPS: OCTEON: Add support for OCTEON III interrupt controller. (diff) | |
| download | linux-dev-c6d2b22eb5211e96e932428bc1183c6ad57d5e54.tar.xz linux-dev-c6d2b22eb5211e96e932428bc1183c6ad57d5e54.zip | |
MIPS: OCTEON: Add SMP support for OCTEON cn78xx et al.
OCTEON chips with the CIU3 interrupt controller use a different IPI
mechanism that previous models.
Add plat_smp_ops for the cn78xx and probing code to choose between the
two types of ops.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/setup.c')
| -rw-r--r-- | arch/mips/cavium-octeon/setup.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 54a214ec33d3..8ffc1f108239 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -43,8 +43,6 @@ #include <asm/octeon/cvmx-mio-defs.h> #include <asm/octeon/cvmx-rst-defs.h> -extern struct plat_smp_ops octeon_smp_ops; - #ifdef CONFIG_PCI extern void pci_console_init(const char *arg); #endif @@ -888,7 +886,7 @@ void __init prom_init(void) #endif octeon_user_io_init(); - register_smp_ops(&octeon_smp_ops); + octeon_setup_smp(); } /* Exclude a single page from the regions obtained in plat_mem_setup. */ |