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authorRalf Baechle <ralf@linux-mips.org>2009-05-27 17:29:37 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-11-02 12:00:01 +0100
commitd30cecbcbe149a36a354757cea835c1bb28689cf (patch)
tree695c69480dfa8e083cf567aad02bef2a5a35cfca /arch/mips/cavium-octeon/smp.c
parentMIPS: Extend COMMAND_LINE_SIZE (diff)
downloadlinux-dev-d30cecbcbe149a36a354757cea835c1bb28689cf.tar.xz
linux-dev-d30cecbcbe149a36a354757cea835c1bb28689cf.zip
MIPS: Don't write ones to reserved entryhi bits.
We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in <asm/mmu_context.h>. We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/smp.c')
0 files changed, 0 insertions, 0 deletions