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| author |   Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:32 -0700 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2017-08-30 00:57:26 +0200 |
| commit | 23cb600e3fd4068697d6fa207848d93e74ec7333 (patch) | |
| tree | ce49d3730432cbdb8e12a3af147b20da9c7e28b9 /arch/mips/include/asm/mips-cpc.h | |
| parent | MIPS: CPS: Use change_*, set_* & clear_* where appropriate (diff) | |
| download | linux-dev-23cb600e3fd4068697d6fa207848d93e74ec7333.tar.xz linux-dev-23cb600e3fd4068697d6fa207848d93e74ec7333.zip | |
MIPS: CPS: Add CM/CPC 3.5 register definitions
Introduce definitions & accessors for a selection of Coherence Manager
(CM) & Cluster Power Controller (CPC) registers that are new with CM
v3.5 & the MIPS I6500. These are primarily registers that will be used
in supporting multiple CPU clusters.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17006/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mips-cpc.h')
| -rw-r--r-- | arch/mips/include/asm/mips-cpc.h | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h index 6cd2847fc95b..1d024cc6ccd8 100644 --- a/arch/mips/include/asm/mips-cpc.h +++ b/arch/mips/include/asm/mips-cpc.h @@ -63,10 +63,12 @@ static inline bool mips_cpc_present(void) #define MIPS_CPC_COCB_OFS 0x4000 #define CPC_ACCESSOR_RO(sz, off, name) \ - CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) + CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \ + CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name) #define CPC_ACCESSOR_RW(sz, off, name) \ - CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) + CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \ + CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name) #define CPC_CX_ACCESSOR_RO(sz, off, name) \ CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \ @@ -91,6 +93,19 @@ CPC_ACCESSOR_RW(32, 0x018, resetlen) /* CPC_REVISION - Indicates the revisison of the CPC */ CPC_ACCESSOR_RO(32, 0x020, revision) +/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */ +CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl) +#define CPC_PWRUP_CTL_CM_PWRUP BIT(0) + +/* CPC_CONFIG - Mirrors GCR_CONFIG */ +CPC_ACCESSOR_RW(64, 0x138, config) + +/* CPC_SYS_CONFIG - Control cluster endianness */ +CPC_ACCESSOR_RW(32, 0x140, sys_config) +#define CPC_SYS_CONFIG_BE_IMMEDIATE BIT(2) +#define CPC_SYS_CONFIG_BE_STATUS BIT(1) +#define CPC_SYS_CONFIG_BE BIT(0) + /* CPC_Cx_CMD - Instruct the CPC to take action on a core */ CPC_CX_ACCESSOR_RW(32, 0x000, cmd) #define CPC_Cx_CMD GENMASK(3, 0) @@ -131,6 +146,9 @@ CPC_CX_ACCESSOR_RW(32, 0x028, vp_run) /* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */ CPC_CX_ACCESSOR_RW(32, 0x030, vp_running) +/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */ +CPC_CX_ACCESSOR_RW(32, 0x090, config) + #ifdef CONFIG_MIPS_CPC /** |