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authorMaciej W. Rozycki <macro@imgtec.com>2016-01-22 05:20:46 +0000
committerRalf Baechle <ralf@linux-mips.org>2016-01-24 01:35:46 +0100
commit733b8bc183f491e8263009edf8ef184fb44a6882 (patch)
tree66645e3de66dd678e42db66113be76c21a0c766a /arch/mips/include/asm/mips-r2-to-r6-emul.h
parentMIPS: math-emu: dsemul: Fix ill formatting of microMIPS part (diff)
downloadlinux-dev-733b8bc183f491e8263009edf8ef184fb44a6882.tar.xz
linux-dev-733b8bc183f491e8263009edf8ef184fb44a6882.zip
MIPS: math-emu: Make microMIPS branch delay slot emulation work
Complement commit 102cedc32a6e ("MIPS: microMIPS: Floating point support.") which introduced microMIPS FPU emulation, but did not adjust the encoding of the BREAK instruction used to terminate the branch delay slot emulation frame. Consequently the execution of any such frame is indeterminate and, depending on CPU configuration, will result in random code execution or an offending program being terminated with SIGILL. This is because the regular MIPS BREAK instruction is encoded with the 0 major and the 0xd minor opcode, however in the microMIPS instruction set this major/minor opcode pair denotes an encoding reserved for the DSP ASE. Instead the microMIPS BREAK instruction is encoded with the 0 major and the 0x7 minor opcode. Use the correct BREAK encoding for microMIPS FPU emulation then. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12174/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mips-r2-to-r6-emul.h')
-rw-r--r--arch/mips/include/asm/mips-r2-to-r6-emul.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mips-r2-to-r6-emul.h b/arch/mips/include/asm/mips-r2-to-r6-emul.h
index 4b89f28047f7..1f6ea8352ca9 100644
--- a/arch/mips/include/asm/mips-r2-to-r6-emul.h
+++ b/arch/mips/include/asm/mips-r2-to-r6-emul.h
@@ -52,7 +52,7 @@ do { \
__this_cpu_inc(mipsr2emustats.M); \
err = __get_user(nir, (u32 __user *)regs->cp0_epc); \
if (!err) { \
- if (nir == BREAK_MATH) \
+ if (nir == BREAK_MATH(0)) \
__this_cpu_inc(mipsr2bdemustats.M); \
} \
preempt_enable(); \