diff options
| author |   Ralf Baechle <ralf@linux-mips.org> | 2009-10-13 23:23:28 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-11-02 12:00:07 +0100 |
| commit | c2ea1d56eaf084c66177eb5658ff4065e79b36ea (patch) | |
| tree | fcc0a634a194dba00f730b54bdf6cf5f0f3b9de1 /arch/mips/include/asm/mmu_context.h | |
| parent | MIPS: Octeon: Use lockless interrupt controller operations when possible. (diff) | |
| download | linux-dev-c2ea1d56eaf084c66177eb5658ff4065e79b36ea.tar.xz linux-dev-c2ea1d56eaf084c66177eb5658ff4065e79b36ea.zip | |
MIPS: Avoid potential hazard on Context register
set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.
Issue found and fixed for head.S by Chris Dearman <chris@mips.com>.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mmu_context.h')
| -rw-r--r-- | arch/mips/include/asm/mmu_context.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index ed331c2e4882..6083db586500 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -16,6 +16,7 @@ #include <linux/smp.h> #include <linux/slab.h> #include <asm/cacheflush.h> +#include <asm/hazards.h> #include <asm/tlbflush.h> #ifdef CONFIG_MIPS_MT_SMTC #include <asm/mipsmtregs.h> @@ -36,11 +37,13 @@ extern unsigned long pgd_current[]; #ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 25); \ + back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif #ifdef CONFIG_64BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 26); \ + back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif |