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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 09:19:02 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 09:19:02 -0700 |
commit | 835a1c092432b3293ba6c4dec45ee6869c6f61fd (patch) | |
tree | a48582e4e4de3a8924b700c5ccaae78cd299cd73 /arch/mips/include/asm/smtc_ipi.h | |
parent | Merge branch 'for-linus' of git://git.alsa-project.org/alsa-kernel (diff) | |
parent | MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq (diff) | |
download | linux-dev-835a1c092432b3293ba6c4dec45ee6869c6f61fd.tar.xz linux-dev-835a1c092432b3293ba6c4dec45ee6869c6f61fd.zip |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (49 commits)
MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq
MIPS: Move ptrace prototypes to ptrace.h
MIPS: Ptrace support for HARDWARE_WATCHPOINTS
MIPS: Scheduler support for HARDWARE_WATCHPOINTS.
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
MIPS: Probe watch registers and report configuration.
MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
MIPS: Add HARDWARE_WATCHPOINTS configure option.
MIPS: Replace use of <asm-generic/uaccess.h> with native implementations.
MIPS: TXx9: Add TX4939 ATA support (v2)
MIPS: Rewrite spinlocks to ticket locks.
MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.
MIPS: IP checksums: Remove unncessary .set pseudos
MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.
MIPS: Move headfiles to new location below arch/mips/include
MIPS: Alchemy: rename directory
MIPS: Optimize get_user and put_user for 64-bit
MIPS: TXx9: Implement prom_free_prom_memory
MIPS: TXx9: Add RBTX4939 board support
MIPS: TXx9: Add TX4939 SoC support
...
Diffstat (limited to 'arch/mips/include/asm/smtc_ipi.h')
-rw-r--r-- | arch/mips/include/asm/smtc_ipi.h | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h new file mode 100644 index 000000000000..8ce517574340 --- /dev/null +++ b/arch/mips/include/asm/smtc_ipi.h @@ -0,0 +1,128 @@ +/* + * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code. + */ +#ifndef __ASM_SMTC_IPI_H +#define __ASM_SMTC_IPI_H + +#include <linux/spinlock.h> + +//#define SMTC_IPI_DEBUG + +#ifdef SMTC_IPI_DEBUG +#include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> +#endif /* SMTC_IPI_DEBUG */ + +/* + * An IPI "message" + */ + +struct smtc_ipi { + struct smtc_ipi *flink; + int type; + void *arg; + int dest; +#ifdef SMTC_IPI_DEBUG + int sender; + long stamp; +#endif /* SMTC_IPI_DEBUG */ +}; + +/* + * Defined IPI Types + */ + +#define LINUX_SMP_IPI 1 +#define SMTC_CLOCK_TICK 2 +#define IRQ_AFFINITY_IPI 3 + +/* + * A queue of IPI messages + */ + +struct smtc_ipi_q { + struct smtc_ipi *head; + spinlock_t lock; + struct smtc_ipi *tail; + int depth; +}; + +static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) +{ + unsigned long flags; + + spin_lock_irqsave(&q->lock, flags); + if (q->head == NULL) + q->head = q->tail = p; + else + q->tail->flink = p; + p->flink = NULL; + q->tail = p; + q->depth++; +#ifdef SMTC_IPI_DEBUG + p->sender = read_c0_tcbind(); + p->stamp = read_c0_count(); +#endif /* SMTC_IPI_DEBUG */ + spin_unlock_irqrestore(&q->lock, flags); +} + +static inline struct smtc_ipi *__smtc_ipi_dq(struct smtc_ipi_q *q) +{ + struct smtc_ipi *p; + + if (q->head == NULL) + p = NULL; + else { + p = q->head; + q->head = q->head->flink; + q->depth--; + /* Arguably unnecessary, but leaves queue cleaner */ + if (q->head == NULL) + q->tail = NULL; + } + + return p; +} + +static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q) +{ + unsigned long flags; + struct smtc_ipi *p; + + spin_lock_irqsave(&q->lock, flags); + p = __smtc_ipi_dq(q); + spin_unlock_irqrestore(&q->lock, flags); + + return p; +} + +static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p) +{ + unsigned long flags; + + spin_lock_irqsave(&q->lock, flags); + if (q->head == NULL) { + q->head = q->tail = p; + p->flink = NULL; + } else { + p->flink = q->head; + q->head = p; + } + q->depth++; + spin_unlock_irqrestore(&q->lock, flags); +} + +static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q) +{ + unsigned long flags; + int retval; + + spin_lock_irqsave(&q->lock, flags); + retval = q->depth; + spin_unlock_irqrestore(&q->lock, flags); + return retval; +} + +extern void smtc_send_ipi(int cpu, int type, unsigned int action); + +#endif /* __ASM_SMTC_IPI_H */ |