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| author |   Huacai Chen <chenhuacai@loongson.cn> | 2022-07-20 18:51:27 +0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2022-07-20 12:09:20 +0100 |
| commit | bcdd75c596c89d7925a3438fde2578ca23a62b06 (patch) | |
| tree | 6a083d272f95ce9572f28aea76b0824d77d293aa /arch/mips/include/asm | |
| parent | irqchip: Add Loongson PCH LPC controller support (diff) | |
| download | linux-dev-bcdd75c596c89d7925a3438fde2578ca23a62b06.tar.xz linux-dev-bcdd75c596c89d7925a3438fde2578ca23a62b06.zip | |
irqchip/loongson-pch-pic: Add ACPI init support
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1658314292-35346-9-git-send-email-lvjianmin@loongson.cn
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-loongson64/irq.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 98ea977cf0b8..55e0dee12cb0 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ #define NR_MIPS_CPU_IRQS 8 #define NR_MAX_CHAINED_IRQS 40 /* Chained IRQs means those not directly used by devices */ #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256) - +#define MAX_IO_PICS 1 #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY #include <asm/mach-generic/irq.h> |