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| author |   Ganesan Ramalingam <ganesanr@broadcom.com> | 2014-04-29 20:07:51 +0530 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2014-05-30 16:49:41 +0200 |
| commit | c065909e47aea3575e51304e7411b46df22b20ca (patch) | |
| tree | 37329d173c186f0b14d27f3f311692c92af6a929 /arch/mips/include | |
| parent | MIPS: Netlogic: Fix XLP9XX pic entry (diff) | |
| download | linux-dev-c065909e47aea3575e51304e7411b46df22b20ca.tar.xz linux-dev-c065909e47aea3575e51304e7411b46df22b20ca.zip | |
MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX
Update PIC frequency calculation for XLP9XX and 2XX processors using
the correct PLL registers. This should work for all possible board
configurations.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6876/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/iomap.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/sys.h | 27 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h index 14b2f5142c6e..805bfd21f33e 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h @@ -120,6 +120,8 @@ #define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2) #define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0) #define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1) +#define XLP9XX_IO_CLOCK_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 2) +#define XLP9XX_IO_POWER_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 3) #define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4) #define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i) diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h index d9b107ffca93..bcb136d224e6 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h @@ -147,6 +147,28 @@ #define SYS_SYS_PLL_MEM_REQ 0x2a3 #define SYS_PLL_MEM_STAT 0x2a4 +/* PLL registers XLP9XX */ +#define SYS_9XX_DMC_PLL_CTRL0 0x140 +#define SYS_9XX_DMC_PLL_CTRL1 0x141 +#define SYS_9XX_DMC_PLL_CTRL2 0x142 +#define SYS_9XX_DMC_PLL_CTRL3 0x143 +#define SYS_9XX_PLL_CTRL0 0x144 +#define SYS_9XX_PLL_CTRL1 0x145 +#define SYS_9XX_PLL_CTRL2 0x146 +#define SYS_9XX_PLL_CTRL3 0x147 + +#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4) +#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4) +#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4) +#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4) + +#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188 +#define SYS_9XX_PLL_CHG_CTRL 0x189 +#define SYS_9XX_CLK_DEV_DIS 0x18a +#define SYS_9XX_CLK_DEV_SEL 0x18b +#define SYS_9XX_CLK_DEV_DIV 0x18d +#define SYS_9XX_CLK_DEV_CHG 0x18f + /* Registers changed on 9XX */ #define SYS_9XX_POWER_ON_RESET_CFG 0x00 #define SYS_9XX_CHIP_RESET 0x01 @@ -170,6 +192,11 @@ #define nlm_get_fuse_regbase(node) \ (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ) +#define nlm_get_clock_pcibase(node) \ + nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node)) +#define nlm_get_clock_regbase(node) \ + (nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ) + unsigned int nlm_get_pic_frequency(int node); #endif #endif |