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| author |   Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:37:16 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 15:37:16 +0100 |
| commit | d7a887a73dec6c387b02a966a71aac767bbd9ce6 (patch) | |
| tree | f32a5f2151b9fe4de1491b601db2e3587d3d52c0 /arch/mips/include | |
| parent | MIPS: Set default pci cache line size. (diff) | |
| download | linux-dev-d7a887a73dec6c387b02a966a71aac767bbd9ce6.tar.xz linux-dev-d7a887a73dec6c387b02a966a71aac767bbd9ce6.zip | |
MIPS: Delete unused function add_temporary_entry.
Only available for R4000 style TLBs anyway and proper ordering of
initialization code made this crude interface unncecessary.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/pgtable-32.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 8a153d2fa62a..d169c07c38ee 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -24,17 +24,6 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask); -/* - * - add_temporary_entry() add a temporary TLB entry. We use TLB entries - * starting at the top and working down. This is for populating the - * TLB before trap_init() puts the TLB miss handler in place. It - * should be used only for entries matching the actual page tables, - * to prevent inconsistencies. - */ -extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - - /* Basically we have the same two-level (which is the logical three level * Linux page table layout folded) page tables as the i386. Some day * when we have proper page coloring support we can have a 1% quicker |