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authorRalf Baechle <ralf@linux-mips.org>2014-11-22 00:22:09 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 22:47:31 +0100
commit15d45cce3a0e0716fa49c768f887c6406dfb91f7 (patch)
treee2235d1a04b61a6c2100f781474e37bda78f5770 /arch/mips/kernel/mips-cm.c
parentMIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT (diff)
downloadlinux-dev-15d45cce3a0e0716fa49c768f887c6406dfb91f7.tar.xz
linux-dev-15d45cce3a0e0716fa49c768f887c6406dfb91f7.zip
MIPS: Replace use of phys_t with phys_addr_t.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/mips-cm.c')
-rw-r--r--arch/mips/kernel/mips-cm.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index f76f7a08412d..85bbe9b96759 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -16,7 +16,7 @@
void __iomem *mips_cm_base;
void __iomem *mips_cm_l2sync_base;
-phys_t __mips_cm_phys_base(void)
+phys_addr_t __mips_cm_phys_base(void)
{
u32 config3 = read_c0_config3();
u32 cmgcr;
@@ -30,10 +30,10 @@ phys_t __mips_cm_phys_base(void)
return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
}
-phys_t mips_cm_phys_base(void)
+phys_addr_t mips_cm_phys_base(void)
__attribute__((weak, alias("__mips_cm_phys_base")));
-phys_t __mips_cm_l2sync_phys_base(void)
+phys_addr_t __mips_cm_l2sync_phys_base(void)
{
u32 base_reg;
@@ -49,13 +49,13 @@ phys_t __mips_cm_l2sync_phys_base(void)
return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
}
-phys_t mips_cm_l2sync_phys_base(void)
+phys_addr_t mips_cm_l2sync_phys_base(void)
__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
static void mips_cm_probe_l2sync(void)
{
unsigned major_rev;
- phys_t addr;
+ phys_addr_t addr;
/* L2-only sync was introduced with CM major revision 6 */
major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
@@ -78,7 +78,7 @@ static void mips_cm_probe_l2sync(void)
int mips_cm_probe(void)
{
- phys_t addr;
+ phys_addr_t addr;
u32 base_reg;
addr = mips_cm_phys_base();