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| author |   Peter Zijlstra <peterz@infradead.org> | 2019-06-13 15:43:19 +0200 |
|---|---|---|
| committer |   Paul Burton <paul.burton@mips.com> | 2019-08-31 11:05:17 +0100 |
| commit | 1c6c1ca318585f1096d4d04bc722297c85e9fb8a (patch) | |
| tree | a3337041a74654c9427dbbaeca1a7a917db996e3 /arch/mips/kernel | |
| parent | mips/atomic: Fix cmpxchg64 barriers (diff) | |
| download | linux-dev-1c6c1ca318585f1096d4d04bc722297c85e9fb8a.tar.xz linux-dev-1c6c1ca318585f1096d4d04bc722297c85e9fb8a.zip | |
mips/atomic: Fix loongson_llsc_mb() wreckage
The comment describing the loongson_llsc_mb() reorder case doesn't
make any sense what so ever. Instruction re-ordering is not an SMP
artifact, but rather a CPU local phenomenon. Clarify the comment by
explaining that these issue cause a coherence fail.
For the branch speculation case; if futex_atomic_cmpxchg_inatomic()
needs one at the bne branch target, then surely the normal
__cmpxch_asm() implementation does too. We cannot rely on the
barriers from cmpxchg() because cmpxchg_local() is implemented with
the same macro, and branch prediction and speculation are, too, CPU
local.
Fixes: e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/syscall.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index b6dc78ad5d8c..b0e25e913bdb 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -132,6 +132,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) [efault] "i" (-EFAULT) : "memory"); } else if (cpu_has_llsc) { + loongson_llsc_mb(); __asm__ __volatile__ ( " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" |