diff options
| author |   James Hogan <james.hogan@imgtec.com> | 2015-07-15 16:17:43 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-09-03 12:07:45 +0200 |
| commit | 3c865dd9c1d64046877112451f13db2cb46d4d28 (patch) | |
| tree | a56689e5e3b8aa1296f81c1640fd71a02d471964 /arch/mips/lib/dump_tlb.c | |
| parent | Documentation/sysrq.txt: Mention MIPS TLB dump (x) (diff) | |
| download | linux-dev-3c865dd9c1d64046877112451f13db2cb46d4d28.tar.xz linux-dev-3c865dd9c1d64046877112451f13db2cb46d4d28.zip | |
MIPS: Refactor dumping of TLB registers for r3k/r4k
The TLB registers are dumped in a couble of places:
- sysrq_tlbdump_single() - when dumping TLB state.
- do_mcheck() - in response to a machine check error.
The main TLB registers also differ between r3k and r4k, but r4k appears
to be assumed.
Refactor this code into a dump_tlb_regs() function, implemented for both
r3k and r4k, and used by both of the above functions.
Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs")
Suggested-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lib/dump_tlb.c')
| -rw-r--r-- | arch/mips/lib/dump_tlb.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 167f35634709..519ededbf9a4 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -13,6 +13,24 @@ #include <asm/pgtable.h> #include <asm/tlbdebug.h> +void dump_tlb_regs(void) +{ + const int field = 2 * sizeof(unsigned long); + + pr_info("Index : %0x\n", read_c0_index()); + pr_info("PageMask : %0x\n", read_c0_pagemask()); + pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi()); + pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0()); + pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1()); + pr_info("Wired : %0x\n", read_c0_wired()); + pr_info("PageGrain: %0x\n", read_c0_pagegrain()); + if (cpu_has_htw) { + pr_info("PWField : %0*lx\n", field, read_c0_pwfield()); + pr_info("PWSize : %0*lx\n", field, read_c0_pwsize()); + pr_info("PWCtl : %0x\n", read_c0_pwctl()); + } +} + static inline const char *msk2str(unsigned int mask) { switch (mask) { |